Curtin, Codecido, Krämer and Bowers (Nano Lett. 2013) showed that gate-induced (field-effect) carriers in multigated silicon nanowires escape ionized-impurity scattering and yield power factors comparable to the best n-type Si nanostructures, and asked whether scaled wires could do substantially better. The open problem is whether field-effect doping in silicon nanowires scaled below the measured tens-of-nanometer cross sections — ultimately into the sub-5 nm regime where one-dimensional subbands survive room-temperature thermal broadening — can deliver a materially higher room-temperature power factor, given the sidewall-roughness, cross-sectional-shape (corner), facet-mobility, and practical-gating constraints raised in follow-up modeling and device work. Atomistic tight-binding/Boltzmann and drift-diffusion simulations predict 2–5× enhancements with sub-nanometer sidewall roughness, but no experiment has demonstrated the effect; the question of how gate-induced carriers, geometry, and quantum confinement jointly determine the achievable power factor and zTzT remains open.

Background

A thermoelectric generator converts a heat flow into electrical power through the Seebeck effect; its material performance is quantified by the dimensionless figure of merit zT=S2σT/κzT = S^{2}\sigma T/\kappa, where SS is the Seebeck coefficient (voltage developed per unit temperature difference), σ\sigma the electrical conductivity, TT the absolute temperature, and κ\kappa the thermal conductivity. The numerator S2σS^{2}\sigma is the power factor. Silicon is abundant, non-toxic and compatible with standard complementary metal–oxide–semiconductor (CMOS) manufacturing, but is a poor thermoelectric mainly because of its high lattice thermal conductivity. Two landmark experiments (Hochbaum et al. and Boukai et al., Nature 2008) showed that rough silicon nanowires suppress κ\kappa through phonon boundary scattering and raise zTzT toward order unity; once κ\kappa approaches its amorphous-like floor, further gains must come from the power factor, which is difficult because SS and σ\sigma are strongly anticorrelated with carrier density (the Mott relation), and because chemical dopants introduce ionized-impurity scattering that lowers mobility precisely at the carrier densities where SS is useful.

Hicks and Dresselhaus (Phys. Rev. B 1993) proposed that reducing dimensionality so that carriers occupy one-dimensional (1D) subbands — discrete transverse quantum-confinement levels spaced by more than the thermal energy kBT≈26k_{\mathrm{B}}T \approx 26 meV at room temperature — sharpens the electronic density of states near the Fermi level and can raise the power factor; in silicon this requires wire diameters of only a few nanometers. Curtin et al. (Nano Lett. 2013) attacked the power factor from a complementary direction: rather than chemical doping, they used field-effect doping — gate-induced inversion charge — in multigated (trigated/gate-all-around) silicon nanowires, in which gates surrounding the wire place a large fraction of its cross section into an induced channel. Because induced carriers are not accompanied by dopant ions, they avoid ionized-impurity scattering; the authors measured gate-modulated SS and σ\sigma and obtained power factors similar to the highest values reported for n-type Si nanostructures, despite charge transport occurring only near the surface of wires a few tens of nanometers across.

The open questions the paper raises, together with follow-up simulation and device literature, identify what stands between that result and a materially higher zTzT: whether smaller-diameter gated wires (below roughly 20 nm) with low sidewall roughness and optimized transport orientation can exceed the measured power factors — the direction stated in the paper's abstract; how the cross-sectional shape and corner rounding of the multigate geometry affect the inversion profile and the local Seebeck coefficient; how sidewall roughness and facet-dependent mobility (for example on {110} sidewall planes) limit the field-effect mobility advantage as wires shrink; how a static, low-leakage, thermally decoupled gate could be realized in a practical generator; and — most fundamentally — whether the 1D-subband (quantum-confinement) power-factor enhancement predicted for sub-5 nm silicon can survive room-temperature thermal broadening in experiment.

Problem Statement

Can field-effect (gate-induced) doping in silicon nanowires scaled below the tens-of-nanometer cross sections measured by Curtin et al. — ultimately into the sub-5 nm regime where 1D subbands are resolved against room-temperature thermal broadening — deliver a room-temperature thermoelectric power factor that exceeds both the 2013 multigated-wire values and chemically doped Si nanostructure benchmarks by at least a factor of two, the lower bound of the 2–5× enhancement predicted by the companion simulations, and thereby a zTzT higher by the same factor when combined with boundary-suppressed lattice thermal conductivity? The problem involves several coupled facets, drawn from the source's stated open direction and from follow-up modeling and device literature, which jointly determine this single objective: (1) whether smaller-diameter multigated wires (below roughly 20 nm) with low sidewall roughness and optimized channel transport orientation can realize power factors significantly exceeding those measured in 2013; (2) how cross-sectional shape and corner rounding quantitatively affect the gate-induced inversion profile, the local Seebeck coefficient, and the net power factor — in particular whether circular or rounded-square sections can eliminate the corner-induced reduction of SS; (3) how far fabrication-induced sidewall roughness and facet-dependent mobility (for example from {110} sidewalls) limit the field-effect mobility advantage as wires are scaled — the authors' companion simulations indicate that a root-mean-square sidewall roughness below about 0.8 nm is necessary for the enhancement — and what fabrication tolerances avoid mobility degradation; (4) how field-effect doping can be integrated into a practical thermoelectric device architecture in which static gate biasing, gate leakage, and gate thermal conduction are managed; and (5) whether quantum-confinement-driven power-factor enhancement can be observed at room temperature in silicon with sub-5 nm diameters, sufficiently narrow diameter distributions, and low scattering that 1D subband effects survive thermal broadening. These facets define the objective jointly rather than as five independent deliverables; the task is resolved by the single determination stated below, not by separately settling each facet. The problem is answered by a rigorous determination of whether the predicted power-factor enhancement over the 2013 gated-wire values and the highest reported n-type Si nanostructure benchmarks is realized or convincingly shown not to be — from room-temperature measurements of the Seebeck coefficient and electrical conductivity on gated silicon nanowires scaled below the 2013 wire cross sections toward the sub-5 nm regime where 1D subbands are resolved and the authors' companion simulations predict confinement-enhanced power factors (with root-mean-square sidewall roughness below about 0.8 nm), where such measurements are available, or, where they are not, from a modeling/literature argument that accounts for the sidewall-roughness, cross-sectional-shape, and gating constraints.

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