Lasting negative composite gate-insulator capacitance in ferroelectric-gate field-effect transistors

Whether the ferroelectric negative-capacitance effect can be used in a field-effect transistor to switch below the Boltzmann limit depends not on the capacitance of the ferroelectric layer itself but on the differential capacitance $C_{ins}$ of the whole gate insulator (dielectric plus ferroelectric layers) becoming and remaining negative during device operation. Eliseev, Morozovska, Yurchenko and Strikha (2022) analyzed a silicon MOSFET with a SiO2/HfO2 gate stack by Landau–Ginzburg–Devonshire theory and finite-element modeling and found a quasi-steady-state negative capacitance of the HfO2 layer near the critical thickness of the size-driven ferroelectric–paraelectric transition, but no combination of material parameters, thicknesses, doping, or bias within their model produced $C_{ins}<0$ in steady or quasi-steady states. Later literature establishes stabilized, even spatially resolved steady-state, negative capacitance of ferroelectric layers in series with dielectrics, and competing explanations exist for experimentally reported sub-60 mV/decade switching; however, no experiment has demonstrated a lasting negative composite gate-insulator capacitance in an operating transistor, and no theory settles whether realistic nonidealities (defect-limited kinetics, multidomain states, interface traps, nonlocal permittivity, dynamical driving) permit or forbid it. The problem — realize a lasting $C_{ins}<0$ in a realistic ferroelectric-gate FET, or prove it impossible in quasi-steady operation — is open.

Background

A metal–oxide–semiconductor field-effect transistor (MOSFET) conducts a drain current whose gate-voltage dependence below threshold is characterized by the subthreshold swing $S$, the gate-voltage change needed for one decade of current change. Because the carrier density injected from the source follows Boltzmann statistics, $S$ cannot fall below $(k_B T/e)\ln 10 \approx 60$ mV/decade at room temperature — the so-called Boltzmann tyranny — which bounds how far the supply voltage, and hence the switching energy of logic circuits, can be reduced.

A ferroelectric has a double-well Landau–Devonshire free energy $F(P)=\alpha P^2/2+\beta P^4/4+\gamma P^6/6$ as a function of polarization $P$ (the electric dipole moment per unit volume of the crystal). Between the two wells, on the S-shaped branch of the polarization–field relation, the inverse differential susceptibility $\partial E/\partial P$ is negative, so an isolated ferroelectric layer would exhibit negative differential capacitance: its voltage drop decreases as its charge increases. Salahuddin and Datta (2008) proposed exploiting this by placing a ferroelectric layer in series with the gate dielectric of a transistor, so that the ferroelectric's negative capacitance amplifies the voltage across the rest of the gate stack and, in principle, allows $S$ below the 60 mV/decade limit. A series positive (linear dielectric) capacitance smaller in magnitude than the ferroelectric's negative capacitance can stabilize the ferroelectric on the negative-slope branch: the combined system then sits at a minimum of total free energy with an overall positive capacitance while the ferroelectric layer itself contributes negative capacitance.

Two decades of work have established the layer-level effect but not the transistor-level one. Transient negative capacitance was measured electrically in ferroelectric capacitors (Khan et al. 2015), negative capacitance of the ferroelectric layers was observed in multidomain ferroelectric–paraelectric superlattices (Zubko et al. 2016) and spatially resolved in the steady state in superlattices of the ferroelectric lead zirconate titanate (PZT) alternating with the paraelectric strontium titanate (STO), where ferroelectric domains (regions of uniform polarization orientation) mediate the stabilized negative-slope state (Yadav et al. 2019), the S-shaped energy landscape was uncovered in hafnium–zirconium oxide (HfZrO, the archetypal silicon-compatible fluorite-structure ferroelectric) with a series dielectric (Hoffmann et al. 2019), and negative differential capacitance was demonstrated in MOS capacitors and transistor gate stacks with 1-nm-class zirconium-doped hafnia, improving on-current, off-current and drain-induced barrier lowering with high endurance (Jo et al. 2023). In parallel, a critical line of work argues that the sub-60 mV/decade slopes repeatedly reported for ferroelectric-gate FETs need not come from quasi-static negative capacitance at all: delayed ferroelectric domain switching reproduces the apparent negative capacitance in pulsed capacitors (Obradovic et al. 2018), a two-step domain nucleation-and-propagation process explains steep slopes (Van Houdt and Roussel 2018), positive non-linear capacitance of the stack can produce them (M. N. K. Alam et al. 2019), and the influential critical review of Alam, Si and Ye (2019) states plainly that the validity of quasi-static negative capacitance remained debated; the major review of Íñiguez, Zubko, Luk'yanchuk and Cano (2019) frames stabilized negative capacitance as a property recovered only in heterostructures with domains. Theory is similarly split: Luk'yanchuk and co-workers proposed domain- and nanodot-based designs intended to realize a stable, reversible, static negative capacitance and emphasized that achieving it in the non-transient, non-hysteretic regime remained a daunting task (Luk'yanchuk et al. 2019, 2022); rigorous Landau–Devonshire analysis maps the dielectric-thickness and field windows within which a ferroelectric layer's negative capacitance is stabilized in a heterostructure (Qin and Li 2024); and the most recent analysis (Ravindran, Ravikumar and Khan 2026) derives the domain-wall-energy conditions under which ideal domain-free negative capacitance would be robust, noting that all experimental evidence to date involves domains.

The question examined here turns on a distinction that is easy to miss. What determines the subthreshold swing is the differential capacitance of the composite gate insulator $C_{ins}$ — the series combination of the dielectric and ferroelectric layers — and not the capacitance of the ferroelectric layer alone. In every stabilized configuration demonstrated so far the total stack capacitance is positive, which is precisely what thermodynamic stability of a passive two-terminal stack requires; the negative capacitance of the ferroelectric layer, however real, does not by itself make $C_{ins}$ negative. Eliseev, Morozovska, Yurchenko and Strikha (2022) analyzed a silicon MOSFET whose gate insulator consists of thin SiO2 and weakly ferroelectric Si-doped HfO2 layers, using Landau–Ginzburg–Devonshire electrostatics (the Landau–Devonshire free-energy description augmented with polarization-gradient terms, the standard continuum theory of ferroelectrics) with Landau–Khalatnikov polarization kinetics (the standard first-order relaxation equation in which the polarization evolves toward the local free-energy minimum), finite-element modeling, and channel charge distributions with ionized dopants and free carriers. They found that a quasi-steady-state negative capacitance of the HfO2 layer is achievable when its thickness is close to the critical thickness of the size-induced ferroelectric–paraelectric transition (below a critical film thickness a ferroelectric loses its spontaneous polarization and becomes paraelectric), but that this state corresponds to a positive capacitance of the whole system; they failed to find any parameters (SiO2 thickness 1–2 nm, HfO2 thickness 5–100 nm, channel widths 1–30 nm, room temperature, varying doping and gate bias) for which $C_{ins}<0$ in either steady or quasi-steady states, so within their model the negative capacitance does not penetrate outside the ferroelectric layer and cannot reduce the swing below the fundamental limit, although the accompanying increase of $C_{ins}$ can lower the swing above the limit and reduce switching losses. Crucially, they observed that thermodynamics forces $C_{ins}>0$ for a two-layer passive capacitor in equilibrium but imposes no such constraint on the three-layer structure that includes the semiconducting channel, so $C_{ins}<0$ is not excluded in principle; and they listed the mechanisms their model omitted — defect-limited switching kinetics (pinning can slow switching from the nanosecond Landau–Khalatnikov scale to microseconds or beyond, breaking quasi-static assumptions), multidomain states and interface trapped charge, nonlocal permittivity and gradient terms that make the series decomposition of layer capacitances non-rigorous, and geometries below experimentally realized minima. Companion works by the same authors give the two sides of the argument: a thermodynamic case that a stable negative capacitance cannot be realized in a MOSFET with a dielectric–ferroelectric insulator and that the ferroelectric's negative capacitance is inherently transient (Strikha and Morozovska 2022), and an analysis of the observability of negative capacitance showing that steady-state layer capacitance is controlled by domain splitting while slow screening charges at the ferroelectric–dielectric interface can generate long-lived transient negative-capacitance signatures (Eliseev et al. 2022, Phys. Rev. B).

Problem Statement

Determine whether the composite gate-insulator differential capacitance of a field-effect transistor with a ferroelectric-containing gate stack — the quantity $C_{ins}$ entering the subthreshold swing together with the semiconductor channel capacitance — can be negative in a lasting steady or quasi-steady operating state (a quasi-steady state is one that evolves only on timescales long compared with every internal relaxation time of the stack, so that it survives arbitrarily slow gate-bias variation). Concretely: either (a) identify a realistic combination of ferroelectric material parameters (e.g., doped-HfO2-class or van der Waals ferrielectric layers — layered crystals with unequal antiparallel polarization sublattices that retain a switchable net polarization — including operation near the size-driven ferroelectric-paraelectric critical thickness, below which a ferroelectric film loses spontaneous polarization), dielectric layer thickness, semiconductor channel doping/profile and geometry, interface trapped charge, defect-limited switching kinetics, multidomain structure, and electrical driving conditions for which the differential capacitance of the combined dielectric-plus-ferroelectric insulator — the quantity $C_{ins}$ entering the subthreshold swing together with the semiconductor channel capacitance — remains negative for arbitrarily slow (quasi-static) gate bias variation — so that the ferroelectric negative capacitance genuinely penetrates outside the ferroelectric layer and the subthreshold swing can fall below the room-temperature Boltzmann limit of 60 mV/decade — or (b) establish, by an argument that explicitly covers the three-layer structure (dielectric/ferroelectric/semiconductor channel) with realistic nonidealities such as interface traps, domain states, defect pinning, and nonlocal permittivity, that $C_{ins}>0$ necessarily in steady and quasi-steady operation, so that the ferroelectric negative capacitance can only improve transistor performance above the fundamental limit (through capacitance enhancement, reduced switching losses and heating) but never below it. Answers must respect the distinction, central to the source work, between the negative capacitance of the ferroelectric layer alone — which is established as real in stabilized heterostructures — and the negative capacitance of the composite insulator, which is what the transistor actually sees.

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