Closing the gap between ab initio upper bounds and realistic devices for ultimately scaled 2D-material CMOS: contacts, oxide disorder, variability, and experimental validation of $\mathrm{HfS}_2/\mathrm{ZrS}_2$ MOSFETs and the dynamically doped FET

Ab initio dissipative DFT-NEGF simulations (density functional theory coupled to non-equilibrium Green's functions) predict that monolayer 2D channels such as $\mathrm{HfS}_2$ and $\mathrm{ZrS}_2$ can sustain high-performance CMOS drive currents down to ~6 nm gate length, and that a proposed dynamically doped field-effect transistor (D2-FET), whose gate electrostatically induces the source/drain doping, extends scaling to ~1 nm gate length with competitive energy-delay product. These are upper bounds computed with ideal ohmic contacts, no surrounding-oxide or defect interactions, and no process variability. The open problem is to determine quantitatively how much of this predicted scaling advantage survives realistic conditions — finite-resistance and Schottky-barrier contacts, disordered oxides, extrinsic defects and variability — through validated realistic modeling and/or experimental demonstration, including whether a D2-FET can be fabricated and operated as simulated and how its doping-gate overlap should be optimized against circuit-level speed and power.

Background

Complementary metal-oxide-semiconductor (CMOS) technology has scaled transistor gate length $L$ for decades, but short-channel effects (SCEs) — loss of gate electrostatic control over the channel, which degrades the subthreshold slope and raises off-state leakage $I_{\text{OFF}}$ — and source-to-drain tunneling (SDT), the quantum leakage of electron wavefunctions through the channel barrier, set a scaling wall for conventional Si, Ge and III–V channels near $L\approx10$ nm, where the required channel thickness of a few nanometers triggers quantum confinement and variability problems. Atomically thin two-dimensional (2D) semiconductors, such as transition-metal dichalcogenides (TMDs — layered compounds of a transition metal and a chalcogen), avoid out-of-plane confinement and offer ultimate electrostatic control. The International Roadmap for Devices and Systems (IRDS) fixes quantitative high-performance (HP) targets — e.g. drive current $I_{\text{ON}}$ at fixed $I_{\text{OFF}}=10$ nA/μm and supply voltage $V_{DD}$, and the contacted gate pitch (CGP, the minimum gate-to-gate spacing that sets transistor footprint). In the source study (Afzalian, npj 2D Materials and Applications 5, 5, 2021), dissipative quantum transport was simulated from first principles: electronic structure from density functional theory (DFT) was transformed into maximally localized Wannier functions (compressed, atom-centered basis orbitals reproducing the DFT bands) and fed into a non-equilibrium Green's function (NEGF) solver including electron–phonon scattering, which is required for a meaningful upper bound because ballistic transport alone overestimates current. The study benchmarked monolayer $\mathrm{MoS}_2$, $\mathrm{WS}_2$, $\mathrm{WSe}_2$, black phosphorus, $\mathrm{HfS}_2$ and $\mathrm{ZrS}_2$ against Si gate-all-around nanowires, and found that the less-explored group-IV TMDs $\mathrm{HfS}_2$ and $\mathrm{ZrS}_2$ — high-mobility, sizeable-gap materials that had received little experimental attention — meet the IRDS-2031 HP $I_{\text{ON}}$ target down to $L\approx6$ nm. It further proposed the dynamically doped FET (D2-FET): instead of chemically doped source/drain extensions, a doping gate placed opposite the contacts overlaps the extensions by $\Delta L$ on each side (doping-gate length $L_{DG}=L+2\Delta L$ without increasing CGP) and electrostatically induces a high carrier concentration in on-state and a near-intrinsic channel in off-state, circumventing the unsolved problem of stable chemical doping in 2D materials and ultra-scaled devices. Simulations showed $\mathrm{HfS}_2$ D2-FETs keep the HP on-current down to $L\approx1$ nm and improve the energy-delay product (EDP, the switching-energy-versus-delay metric of a loaded CMOS inverter) when scaling to effectively $L=0$ nm at CGP = 22 nm. However, these results are explicit upper bounds: ohmic contacts were assumed, interactions with surrounding oxides, extrinsic defects/disorder and process variability were neglected, spin–orbit coupling was not included in the DFT step, the EDP analysis used one fixed $\Delta L$, and neither $\mathrm{HfS}_2/\mathrm{ZrS}_2$ devices at these dimensions nor any D2-FET have been demonstrated experimentally. Since 2021, parts of this gap have been attacked in isolation: semimetal contacts to monolayer $\mathrm{MoS}_2$ reached contact resistivities on the order of $10^{2}\ \Omega\cdot\mu\mathrm{m}$ experimentally (Shen et al., Nature, 2021); ab initio contact studies showed sub-100 $\Omega\cdot\mu\mathrm{m}$ is reachable for 2D metals with electrostatic doping, at a ~25% current penalty versus ideal ohmic contacts (Duflou et al., 2023), and defined the quantum tunneling limit of contact scaling below ~10 nm contact length (Kim et al., 2026); first-principles work quantified how disordered amorphous oxides degrade monolayer TMD mobility by roughly an order of magnitude versus the ideal limit (Dossena et al., 2025). What no work has done is integrate these non-idealities into a quantitative re-assessment of the ultrascaled $\mathrm{HfS}_2/\mathrm{ZrS}_2$ MOSFET and D2-FET predictions, or validate either experimentally.

Problem Statement

Determine, by validated realistic modeling and/or experimental demonstration, how much of the predicted sub-10-nm scaling and energy-delay advantage of monolayer $\mathrm{HfS}_2/\mathrm{ZrS}_2$ MOSFETs and of the dynamically doped FET (D2-FET) survives realistic non-ideal conditions. Concretely: (1) re-assess the $I_{\text{ON}}$/$I_{\text{OFF}}$, subthreshold-slope, and energy-delay-product predictions of the ideal-ohmic-contact, oxide-free, defect-free atomistic simulations once contacts have finite resistance and Schottky barriers (including the metal-induced-gap-states tunneling regime below ~10 nm contact length), the channel interfaces with realistic (disordered or crystalline) gate/spacer dielectrics, and extrinsic defects plus process variability are included — identifying which non-ideality dominates the degradation and whether IRDS high-performance targets are still met at gate lengths of ~6 nm and below; (2) establish whether a D2-FET, in which a doping gate overlapping the source/drain extensions by $\Delta L$ per side (doping-gate length $L_{DG}=L+2\Delta L$ at unchanged contacted gate pitch) electrostatically induces the extension doping, can be fabricated with process-compatible alignment and isolation of the doping gate and operated as simulated — near-intrinsic channel in off-state, high dynamic carrier concentration in on-state — at ultrascaled dimensions; and (3) optimize the $\Delta L$ trade-off between on-current gain and intrinsic gate capacitance at the circuit level (inverter energy-delay product versus footprint, including lithographic and layout constraints such as spacer and gate-pitch rules, beyond the single fixed $\Delta L=4$ nm analyzed in the source study). These three components jointly serve one objective: replacing the ab initio upper bound with a defensible realistic bound — or an experimental realization — for ultimately scaled 2D-material CMOS and the dynamically doped transistor architecture. A defensible quantitative result on any one of components (1)–(3) is a partial answer; the objective is completely answered either by validated modeling of components (1) and (3) and of component (2)'s operating-physics clause together with experimental or process/fabrication evidence for component (2)'s fabrication clause, or by an experimental demonstration of a monolayer $\mathrm{HfS}_2/\mathrm{ZrS}_2$ high-performance transistor or of D2-FET operation at scaled pitch, with quantified contact resistance and interface quality. Because fabricability cannot be established by modeling alone, a validated modeling bound that omits component (2)'s fabrication clause is a partial answer.

References

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