Can a ferroelectric negative-capacitance FET act as a genuine steady-state steep-slope logic switch?

The question, posed by Cao and Banerjee (Nature Communications, 2020), is whether a ferroelectric negative-capacitance field-effect transistor (NC-FET) can genuinely serve as a steep-slope logic switch: achieving steady-state, hysteresis-free subthermionic subthreshold swing (below 60 mV/decade at room temperature) over a useful current range — as opposed to reported steep slopes arising from transient polarization dynamics or charge-trapping artifacts, or the effect being confined to saving gate-voltage losses (the role for which the source separately requires a GHz-capable polarization response). The problem remains open.

Background

A metal-oxide-semiconductor field-effect transistor (MOSFET) switches by electrostatically modulating the potential of its channel. Its gate-to-channel voltage coupling is limited by the Boltzmann statistics of thermally injected carriers: the subthreshold swing, $SS = dV_G/d\log_{10} I_D$, cannot fall below $(k_BT/q)\ln 10 \approx 60$ mV per decade of drain current at room temperature (the thermionic or Boltzmann limit). Because switching energy scales roughly with the square of the supply voltage, this 60 mV/dec floor blocks further voltage scaling of CMOS logic.

Ferroelectrics offer a proposed escape. A ferroelectric is a material with a switchable spontaneous polarization $P$; its energy landscape, described by Landau theory as a double-well function of $P$, contains an unstable region where $dP/dE < 0$ — a negative capacitance. Salahuddin and Datta (2008) proposed that inserting a ferroelectric (FE) layer in the gate stack of a transistor, in series with the positive gate-oxide and channel capacitances, could stabilize this negative-capacitance (NC) state by capacitance matching: the series positive capacitance holds the FE on the steep, negative-slope part of its polarization–electric-field curve, amplifying the internal gate voltage and in principle allowing $SS < 60$ mV/dec without changing carrier statistics. Steady-state NC has been directly observed in model systems — e.g., spatially resolved by electron microscopy in epitaxial perovskite superlattices (Yadav et al., 2019) — and ferroelectric HfO$_2$–ZrO$_2$ (HZO) thin films made the concept nominally CMOS-compatible, producing many reported sub-60 devices (e.g., Si et al., 2018, MoS$_2$ NC transistors).

Cao and Banerjee (2020) re-examined these claims with an analytical model of the NC-FET capacitance network. Writing the channel quantum capacitance $C_Q$ (the finite channel charge response to a potential shift, $C_Q = q^2 \times$ channel density of states) as part of a voltage-divider capacitance $C_{div}$ that also contains interface-trap, depletion, and source/drain geometrical capacitances, they showed that the minimum hysteresis-free subthreshold swing is

$SS_{\min} = 60\,\text{mV/dec} \times \frac{C_Q}{C_Q + C_{div,<V_{th}}},$

attained when the magnitude of the NC capacitance is matched to the above-threshold MOS capacitance. Three consequences follow. First, well-designed modern MOSFETs (low traps, low doping, good electrostatics) gain almost nothing: with a large channel density of states (DOS), hysteresis-free sub-60 swing is essentially unattainable for Si and barely for MoS$_2$; only low-DOS channels operating near the quantum-capacitance limit (e.g., high-indium-content III–V compounds, or monolayer Germanane — hydrogenated germanene — predicted to reach about 39 mV/dec) leave a usable design window. Second, steep slopes reported in the literature appear mostly at current levels near the noise floor and are plausibly artifacts of transient ferroelectric polarization dynamics that depend on the voltage sweep rate and direction rather than steady-state NC. Third, a more practical role of NC may be saving subthreshold and overdrive voltage losses — but only if the intrinsic polarization switching speed can be raised enough for the NC layer to function at GHz logic frequencies.

This reframing was contested and consequential: the field's leading ferroelectronics groups acknowledged a theory–experiment gap, controversy, and the absence of robust characterization protocols and reference devices (Nature Electronics, 2020). The unresolved scientific question is therefore two-sided: either realize and rigorously authenticate a steady-state, hysteresis-free, subthermionic NC-FET, or establish by general analysis the physical limits of the effect — that genuine steep-slope switching cannot be practically realized in devices of the stated class — and quantify what NC can deliver, e.g. the voltage-loss-saving role subject to the source's GHz polarization-speed proviso.

Problem Statement

Determine whether a ferroelectric negative-capacitance field-effect transistor can function as a genuine steep-slope logic switch. Specifically, establish whether a stabilized ferroelectric gate layer can endow a transistor (with a channel operating in the quantum-capacitance limit, $C_Q < C_{OX}$ as defined in the source, in a gate stack compatible with CMOS-class fabrication) with all of the following, jointly:

1. subthreshold swing below 60 mV/decade at room temperature, sustained over a practically useful drain-current range well above the off-state current and the measurement noise floor, rather than only near the off-state current;
2. the sub-60 swing measured in steady state — invariant to gate-voltage sweep rate, sweep direction, and pulse timing — so that it is attributable to stabilized negative capacitance rather than to transient ferroelectric polarization dynamics;
3. hysteresis-free operation between forward and reverse gate sweeps — in the source's stabilization sense, a positive slope $S$ over the entire $I_D$–$V_G$ curve at the capacitance-matched operating point ($|C_{NC}| = C_{MOS,>V_{th}}$) — consistent with the ferroelectric remaining on the stabilized negative-capacitance branch of its polarization–electric-field curve rather than switching between the two wells of its Landau double-well energy landscape.

GHz-capable ferroelectric polarization response is not a conjunct of this steep-slope target; per the source, it is the separately recognized condition for the alternative practical role of NC as a voltage-loss saver.

An affirmative answer is a realized device — whether fabricated by the solver or authenticated from the literature — together with robust characterization — reported with respect to reference devices, as the 2020 Nature Electronics editorial and the Hoffmann et al. comment call for — sufficient to exclude transient ferroelectric polarization dynamics and charge-trapping artifacts as alternative explanations. Sweep-rate- and pulse-dependent transfer measurements, matched control devices (the same stack with the ferroelectric replaced by a paraelectric — a non-ferroelectric dielectric — of the same equivalent oxide thickness, i.e. the same areal gate capacitance), and frequency-domain gate-stack response are illustrative source-mentioned means of authentication, not mandatory elements. A negative answer is a general device-physics analysis establishing the physical limits of the effect: that genuine steady-state, hysteresis-free, room-temperature subthermionic switching cannot be practically realized for every realistic stabilized ferroelectric coupled to the stated class's field-effect-transistor capacitance network (quantum capacitance, interface traps, dielectric layer) in a manufacturable CMOS-class gate stack, and quantifying the achievable bound. Since the source's quasi-static analysis already concludes that hysteresis-free sub-60 mV/dec is achievable in principle in the quantum-capacitance limit, the negative target concerns practical realizability rather than the quasi-static conjunction the source affirmatively answers; such a result would confirm that the effect's practical value lies in saving gate-voltage losses (subject to the source's GHz polarization-speed proviso) and boosting transconductance rather than in steep-slope switching.

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