On-chip cryogenic multiplexed readout of Si/SiGe quantum-dot arrays: switch speed, magnetic-field robustness, fabrication yield, and validated readout fidelity at scale

A 2024 demonstration monolithically integrated depletion-mode FET multiplexers with 16 Si/SiGe quantum-device zones on one chip, operating at about 2 K and fields up to ~6 T with a nearly tenfold wiring reduction, and proposed a serial-readout architecture for large silicon qubit arrays in which on-chip switches route each qubit's charge-sensor signal in turn to an off-chip cryogenic amplifier. The demonstration left the architecture uncompleted: the measured multiplexer rise time (176 microseconds, dominated by ~14.4 nF of inter-routing-layer capacitance) caps serial readout at roughly 30 qubits for the assumed 10 ms readout-state lifetime; the switches develop Hall voltages and quantum-Hall-like signatures near depletion at high field; 4 of 16 zones failed; and readout fidelity at array scale was only simulated. The open problem is to close these gaps together — reduce the switch/RC settling time by roughly an order of magnitude or more, make switch magnetotransport benign across the required field and bias ranges, achieve near-unity zone yield, and measure, not just simulate, high-fidelity multiplexed readout of a qubit array under realistic noise, drift, amplifier, and variability constraints. No existing cryogenic multiplexing demonstration has shown multiplexed high-fidelity qubit readout at multi-tesla fields.

Background

Spin qubits in gate-defined quantum dots are a leading candidate for large-scale quantum computation because they exploit the same silicon fabrication technology as classical microprocessors. A gate-defined quantum dot is a small electrostatic trap for electrons formed by metallic electrodes ('gates') on top of a semiconductor; in Si/SiGe heterostructures the electrons reside in a strained silicon quantum well forming a two-dimensional electron gas (2DEG). The state of a spin qubit is typically read out through a nearby charge sensor (a quantum dot whose current is sensitive to single-electron occupancy) using Pauli spin blockade (PSB), a protocol in which the singlet and triplet states of a double dot map to different charge configurations and hence different sensor signals. The readout state has a finite lifetime $T_1$ — about 10 ms in typical Si/SiGe double dots — before it relaxes and erases the information.

As the qubit count grows, the number of input-output (I/O) wires needed to address gates, ohmic contacts, and sensors — currently roughly proportional to the number of qubits — collides with the limited cooling power and physical space of cryogenic refrigerators. This is the interconnect bottleneck. Classical microprocessors solved the analogous problem by multiplexing, sharing each physical wire among many devices; the empirical power-law relation between device count and I/O count is known as Rent's rule. Bringing this idea inside the cryostat, onto the same chip as the qubits, is difficult because the switching electronics must work at kelvin-scale temperatures, in the multi-tesla magnetic fields that many spin-qubit platforms require (in Si/SiGe these fields also produce the quantum Hall effect — the quantization of the 2DEG's transverse resistivity in units of $h/e^2$ — which distorts the behavior of any 2DEG-based circuit element), and without adding heat, noise, or fabrication steps that degrade the qubits.

Wolfe et al. (2024) took a major step in this direction. They monolithically integrated depletion-mode field-effect transistor (FET) switches — fabricated in the same Si/SiGe wafer and in the same plane as the quantum devices — into a 4-bit multiplexer addressing 16 'construction zones' containing Hall-bar test devices (bar-shaped 2DEG devices used to measure longitudinal and transverse resistivity). The whole system operated at about 2 K in a pumped 4He cryostat, the integer quantum Hall effect was observed in the array at fields up to about 6 T, and the wiring was reduced nearly tenfold (16 lines replacing 112). Grounding the inactive zones removed the voltage drift and hysteresis that had plagued the earlier on-chip-switch demonstration of Ward et al. (2013), whose floating switch drains charged to unknown voltages. Building on this test bed, and on the switched-capacitor (sample-and-hold) circuits that Xu et al. (2020) integrated with Si/SiGe quantum dots — circuits in which a capacitor holds a gate voltage after it is set once, so many gates can share one line — the authors proposed a readout architecture in which the ohmic contacts of $N$ qubit arrays are routed one at a time through the on-chip multiplexer to an off-chip cryogenic amplifier, and each qubit is read by PSB in series. Their simulations used a conservative readout-state lifetime $T_1=10\ \mathrm{ms}$ and a per-qubit integration time $t_{\mathrm{int}}=2\tau$, where $\tau=176\ \mu\mathrm{s}$ is the measured rise time of the multiplexed readout signal (dominated by about 14.4 nF of capacitance between the two metal routing layers), and showed that the attainable array size $N$ is set by the requirement that the total serial measurement time $N t_{\mathrm{int}}$ not exceed $T_1$. The authors identified two speed levers: reducing the routing-layer parasitic capacitance, or using SiGe MODFETs (modulation-doped field-effect transistors, in which carriers are supplied by a remote doped layer, giving high mobility and fast switching at cryogenic temperature) as the switch elements.

What the demonstration did not do is exactly the open problem. The multiplexer was exercised for device characterization, not qubit readout: 12 of the 16 zones functioned (two would not turn on, one showed no transverse voltage, one had a broken drain contact); the switch FETs themselves develop Hall voltages and quantum-Hall-like signatures when biased near depletion at high field and must be operated well above threshold to stay benign, a constraint the authors flag as central for future multiplexer designs; the 176 µs rise time caps serial readout at $N$ of order $T_1/(2\tau)\approx 30$ for the assumed $T_1$; and the readout fidelity itself was simulated with conservative assumptions rather than measured at array scale under realistic noise, drift, amplifier limitations, and device-to-device variability. Adjacent multiplexing efforts — cryo-CMOS multiplexers integrated with silicon quantum dots (CMOS, complementary metal-oxide-semiconductor; cryo-CMOS denotes such circuits engineered for cryogenic operation), nanowire demultiplexer arrays, a 1024-dot rapid-characterization chip with an on-chip high-frequency analog multiplexer, and millikelvin cryo-CMOS bias demultiplexing — advance individual components of the wiring problem without demonstrating multiplexed qubit readout in the regime silicon spin qubits require.

Problem Statement

The problem left open by Wolfe et al. (2024) is to turn their monolithic Si/SiGe multiplexer platform — a characterization test bed of 16 switched device zones operating at about 2 K and fields up to ~6 T with a nearly tenfold wiring reduction — into a working readout architecture for a large quantum-dot qubit array. Concretely, one must design, fabricate, and experimentally demonstrate on-chip cryogenic multiplexed readout that simultaneously satisfies four jointly required conditions:

1. Speed and capacitance: the multiplexer rise time $\tau$ must be short enough that serial readout of $N$ qubits, each taking an integration time $t_{\mathrm{int}}\approx 2\tau$, completes within the readout-state lifetime $T_1$ (i.e., $N t_{\mathrm{int}}\lesssim T_1$). The demonstrated $\tau=176\ \mu\mathrm{s}$, dominated by ~14.4 nF of inter-routing-layer capacitance, restricts $N$ to roughly $T_1/(2\tau)\approx 30$ for the assumed $T_1=10\ \mathrm{ms}$; useful array sizes (hundreds of qubits and beyond) require at least an order-of-magnitude reduction of $\tau$ — concretely $\tau \lesssim 16\ \mu\mathrm{s}$, so that $N \gtrsim 300$ fits within $T_1=10\ \mathrm{ms}$ — through lower routing-layer parasitic capacitance or faster switch transistors such as SiGe MODFETs, without compromising the other conditions.

2. Magnetic-field robustness: the switches must remain electrically benign — introducing no Hall-voltage offset and no quantum-Hall-induced distortion of the routed sensor signal large enough to reduce the condition-4 readout fidelity below its target — over the full magnetic-field and bias range in which the qubits operate (the source demonstration reaches the quantum Hall regime at 5–6 T). Switch FETs biased near depletion develop Hall voltages and quantum-Hall-like distortions of the routed signals; the present mitigation — operating well above threshold — must not require gate voltages incompatible with the surrounding devices.

3. Fabrication yield: at least 99% of the construction zones on the chip must be functional; in the demonstration 4 of 16 zones failed (two would not turn on, one showed no transverse voltage, one had a broken drain contact).

4. Validated fidelity at scale: high-fidelity readout (single-shot readout fidelity at least 99%), benchmarked with the field's standard protocols for spin-qubit readout such as Pauli spin blockade, must be measured — not only simulated — for a multiplexed array of $N$ qubits at useful array scale (hundreds of qubits and beyond — far beyond the roughly $T_1/(2\tau)\approx 30$ serial-readout cap of the demonstrated $\tau=176\ \mu\mathrm{s}$) under realistic noise, drift, amplifier limitations, and device-to-device variability, with the serial-readout timing constraint above verified on the same hardware.

The problem is complete when an integrated chip demonstrates all four conditions together for a quantum-dot qubit array at useful array scale (hundreds of qubits and beyond — far beyond the roughly 30-qubit serial-readout cap imposed by the demonstrated $\tau=176\ \mu\mathrm{s}$); advances on any single condition in isolation (e.g., a faster multiplexer used only to characterize non-qubit devices, multiplexed DC gate biasing without readout, or multiplexed high-fidelity readout demonstrated only for a few qubits within the cap the demonstrated rise time already permits) constitute progress but not resolution.

References

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