A linear array of eight silicon spin qubits fabricated in a 300 mm CMOS foundry process demonstrated coherent single-qubit control of all qubits and one characterized CZ-type two-qubit gate, but the Heisenberg exchange interaction failed to turn on smoothly in three of the four double-dot unit cells, and the device was strictly one-dimensional. The open problem is to establish the device design (gate pitch and geometry), electron-occupancy choice, and tuning protocol under which on-demand inter-qubit exchange — smooth, continuous turn-on enabling calibrated entangling gates — operates in every unit cell of a foundry-fabricated SiMOS array; extending coherent, synchronously controlled multi-qubit operation to higher-connectivity (bi-linear or sparse two-dimensional) foundry layouts is the further architectural direction for the platform. As of August 2026 the problem remains open: foundry unit cells with above-99% two-qubit-gate fidelity and EUV-patterned foundry devices with reproducible exchange turn-on exist only at the isolated-unit-cell scale, and inter-unit-cell entanglement has been demonstrated only in an academically fabricated SiMOS four-qubit device.

Background

Silicon spin qubits encode quantum information in the spin of individual electrons confined in gate-defined quantum dots — nanoscale electrostatic traps at a silicon/silicon-dioxide interface in the SiMOS (silicon metal–oxide–semiconductor) variant. Plunger gates (P) accumulate the dots, barrier gates (J) tune the tunnel coupling between neighbors, and single-electron transistors (SETs) sense nearby charge movement for readout. Because silicon can be isotopically purified to mostly the zero-nuclear-spin isotope 28^{28}Si, spin coherence times are long, and the platform is compatible with standard CMOS manufacturing, motivating its pursuit on 300 mm industrial foundry lines (Intel; imec with UNSW/Diraq). Qubit pairs are commonly operated as double-quantum-dot (DQD) 'unit cells': two dots whose spins are initialized by relaxation and read out via Pauli spin blockade (the prohibition on charge motion through spin-polarized triplet states, sensed by the SET), and individually addressed by electron spin resonance (ESR) through an on-chip microwave antenna, exploiting small device-to-device differences in the electron g-factor to separate the qubits' resonance frequencies. Two-qubit entangling gates rely on the Heisenberg exchange interaction — an electrically controlled coupling JJ between neighboring spins, tuned by the barrier-gate voltage — from which controlled-phase (CZ) gates are built; a smooth, approximately exponential turn-on of JJ with gate voltage is needed for the exchange to be calibrated into a usable gate, whereas an abrupt onset caused by charge rearrangement (for example an electron shuttling into a spurious 'J-dot' that forms under a wide barrier gate) is not usable. Foundry-fabricated SiMOS devices have already shown >99% fidelity in single- and two-qubit operations in isolated unit cells with reduced gate size and pitch (Steinacker et al., Nature 2025), following earlier 300 mm demonstrations at Intel (Zwerver et al., 2022) and the fabrication of 12-dot linear arrays on Intel's 300 mm line without array-wide entangling operation (George et al., 2024). The eight-qubit device of Nickl et al. ( imec 300 mm process, 90 nm gate pitch — larger than optimal for exchange) extended this to a four-unit-cell linear array: all eight qubits were coherently controlled, with Ramsey dephasing times T2∗T_2^* up to 41(2) μ\mus and Hahn-echo times up to 1.31(4) ms and cascaded readout of the central cells. But only the P1–P2 cell showed a smooth exchange turn-on (33.69(1) dec/V at its (9,3) electron occupation), enabling a characterized CZ operation; the other cells showed no exchange turn-on before charge rearrangement, except P7–P8 which showed an abrupt, spurious-dot-mediated onset. Increasing the electron number per dot enlarges the qubit wavefunction (valence electrons occupy larger p-type orbitals) and hence the overlap that generates exchange, but it reduces charging energies, brings low-lying excited states into play, and multiplies tuning complexity — an unresolved occupancy trade-off. Finally, fault-tolerant architectures require connectivity beyond a strictly linear chain (bi-linear or sparse two-dimensional arrays), which in turn requires scalable synchronous control, resonator- or global-field driving, and readout scaling; adjacent platforms show what array-level operation looks like — universal control of six academic Si/SiGe qubits (Philips et al., 2022), six-qubit circuits on that platform (Fernández de Fuentes et al., 2026), and an 18-qubit germanium 2×N modular array with CZ gates and a GHZ state (Dijkema et al., 2026) — but none of these is a foundry SiMOS device.

Problem Statement

The problem, as left open by the eight-qubit foundry SiMOS demonstration (Nickl et al., 2026), is to make on-demand inter-qubit exchange a routine, array-wide capability of the 300 mm foundry SiMOS platform, and to carry coherent operation beyond strictly linear arrays. Concretely, the open problem has as its core two jointly linked requirements serving this single objective: (1) identify the device-design changes — reduced gate pitch and gate dimensions, altered gate geometry, and/or controlled increases in electron occupancy per dot — under which the Heisenberg exchange interaction between each unit cell's qubit pair turns on smoothly and continuously with barrier-gate voltage (an approximately exponential, calibratable onset rather than an abrupt or spurious-dot-mediated one) in every unit cell of a foundry-fabricated multi-qubit SiMOS array (as exemplified by, but not limited to, the four-unit-cell/eight-qubit generation), and establish calibrated CZ-type entangling-gate operation for the qubit pair of every cell; and (2) resolve the occupancy trade-off — larger qubit wavefunctions from higher electron number versus expanded tuning complexity, lower charging energies, and low-lying excited states — into a documented, reproducible occupancy and tuning strategy that works across all cells, including suppression of intermediate J-dot formation under barrier gates. Beyond this core, a further architectural direction for the platform is: (3) extending coherent, synchronously controlled multi-qubit operation to foundry-fabricated layouts with higher-than-linear connectivity, such as bi-linear or sparse two-dimensional arrays as required by proposed quantum-error-correction architectures, together with the associated control-scheme changes (e.g., resonator-based or global-field driving) and device-level variability management (g-factor spread, antenna-induced Larmor shifts); progress on this direction is partial progress toward the broader platform goal, not an alternative to the array-wide exchange core. The deliverable is a written answer: a concrete device design and a fully specified tuning protocol, supported by analytic and/or simulation evidence, addressing requirements (1) and (2) as a general, scalable argument rather than a recipe confined to one device instance. The objective is array-wide: results confined to isolated unit cells or a single qubit pair do not resolve the problem.

References

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