Amorphous InGaZnO4 (a-IGZO) thin-film transistors (TFTs) show a large gate-voltage hysteresis in their transfer characteristics when the channel is left unannealed (a forward-reverse voltage shift of about 4 V in the devices studied by Kimura et al., 2008), which disappears after a 300 °C air anneal. Kimura et al. extracted the energy-resolved trap density N(E)N(E) from low-frequency capacitance-voltage (C-V) curves and found that the anneal-induced reduction of N(E)N(E) can quantitatively account for only about 1 V of the approximately 4 V shift; moreover, the shallow states they detect 0.1-0.3 eV below the conduction-band edge EcE_c should respond too quickly to cause hysteresis in slow, low-frequency scans. The problem, still open, is to identify and quantify the microscopic (chemical/structural) nature, location, and charging/discharging dynamics of the centers actually responsible for the hysteresis in a-IGZO TFTs, and to settle the related methodological question of how much of the C-V-extracted density near EcE_c is genuine localized trap density rather than conducting-state (free-carrier) density. Later literature supplies several candidate mechanism classes - charge trapping at the gate-insulator/channel interface and in the gate insulator with response times spanning the measurement range, metastable oxygen vacancies whose transition states change on charge/discharge cycles, and water- or hydrogen-related species - together with decomposition and mitigation tools, but no work quantitatively closes the attribution for these (or general) a-IGZO devices.

Background

A thin-film transistor (TFT) is a field-effect transistor in which the conducting channel is a thin film (here amorphous InGaZnO4, a-IGZO) separated from the gate electrode by an insulating gate dielectric (here SiO2). TFTs based on a-IGZO, an amorphous oxide semiconductor, are the workhorse backplane technology for active-matrix liquid-crystal and organic light-emitting-diode (OLED) displays because they combine high electron mobility with low-temperature, large-area deposition. The density of electronic states in the band gap of the a-IGZO channel - 'trap' or subgap states that can capture and release electrons - controls the threshold voltage, subthreshold swing, and stability of these transistors, so measuring it in an actual device is a central problem of oxide electronics.

Kimura, Nakanishi, Nomura, Kamiya, and Hosono (Applied Physics Letters 92, 133512, 2008) extracted the energy-resolved density of states N(E)N(E) (in units of cm−3eV−1\mathrm{cm^{-3}eV^{-1}}) directly from the low-frequency (0.1-0.5 Hz) capacitance-voltage (C-V) characteristics of the TFTs, using a Poisson-equation fitting algorithm adapted to the TFT boundary conditions (the back surface of the channel is electrically floating, unlike a metal/insulator/semiconductor capacitor with a fixed bulk potential). The surface potential ϕs\phi_s, the band bending at the gate-dielectric/channel interface, is obtained from the measured gate capacitance by integration, and N(E)N(E) follows from the charge density ρ=−q∫0ϕN dϕ\rho = -q\int_0^{\phi} N\,d\phi that reproduces the measured C-V curve. They found N(E)N(E) approximately flat deep in the gap at 1.7×1016 cm−3eV−11.7\times10^{16}\ \mathrm{cm^{-3}eV^{-1}}, rising on approach to the conduction-band edge EcE_c; a parallel study (Hsieh et al., 2008) modeled the same subgap density of states with a two-step function in device simulations.

A key observation of the 2008 paper concerns hysteresis: when the gate voltage is swept forward and back, the drain-current/gate-voltage transfer curve of the unannealed device traces two different branches separated by a large voltage window (about 4 V for the devices studied). Post-annealing at 300 °C for 1 h in air simultaneously reduces the extracted trap density near EcE_c and eliminates the hysteresis, together with improving the subthreshold swing and mobility. However, the authors noted a quantitative and a qualitative mismatch. Quantitatively, the measured change in N(E)N(E) would account for only about a 1 V shift, not the observed 4 V. Qualitatively, the shallow states detected about 0.1-0.3 eV below EcE_c would normally be 'fast' states, exchanging charge on time scales much shorter than the slow low-frequency measurement, and therefore should not produce hysteresis in such slow scans at all. Slow states with release times comparable to or longer than the measurement time are the classical cause of hysteresis (in analogy with amorphous-silicon TFTs), so the origin of the large slow hysteresis in unannealed a-IGZO TFTs must lie in centers other than, or in addition to, the extracted near-edge states - candidates include slow charge trapping at the gate-dielectric/channel interface or in the gate insulator, mobile ionic species, water- or hydrogen-related species, or other structural/chemical defects. A related methodological limitation acknowledged in the source is that near EcE_c the Fermi level approaches or enters the conduction band, so the extraction, which attributes all charge to localized states, may mix conducting-state (free-electron) density with genuine localized trap density.

Later work (reviews by Kamiya et al., 2010, and Fortunato et al., 2012) places hysteresis within the broader instability family of a-IGZO TFTs (bias stress, illumination stress, ambient effects), for which several coexisting mechanisms have been proposed but no single quantitative microscopic attribution has been established.

Problem Statement

Identify and quantify the microscopic origin of the gate-voltage hysteresis in amorphous-InGaZnO4 (a-IGZO) thin-film transistors. In the source devices, the forward-reverse transfer-curve separation of the unannealed TFTs is about 4 V, while the anneal-induced change in the capacitance-voltage (C-V)-extracted trap density N(E)N(E) accounts for only about 1 V, and the detected shallow states 0.1-0.3 eV below the conduction-band edge EcE_c are expected to be too fast to cause hysteresis in slow, low-frequency (sub-Hz) measurements. The problem is to determine the chemical/structural identity and spatial location of the centers responsible (for example, slow charge trapping at the gate-dielectric/channel interface or inside the gate insulator, mobile ionic species, water- or hydrogen-related species, or metastable oxygen-vacancy configurations), and to characterize their charging/discharging dynamics (response times, activation energies, and charge magnitudes) well enough to quantitatively reproduce the observed hysteresis window and its disappearance upon thermal annealing. It includes the related methodological question of separating the conducting-state (free-carrier) contribution from the genuine localized-trap contribution in the low-frequency C-V-extracted density N(E)N(E) near EcE_c, and extending such trap-density extraction to faster measurement regimes in which hysteresis-relevant states are resolved. The target is the physical attribution - the chemical/structural identity and spatial location of the centers, and their charging/discharging dynamics, quantitatively reproducing the observed hysteresis window and its disappearance upon thermal annealing - together with the methodological decomposition of the low-frequency C-V-extracted density N(E)N(E) near EcE_c into its conducting-state (free-carrier) and genuine localized-trap contributions; extending the extraction to faster measurement regimes is a related extension of the same question.

References

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