The magnetoelectric spin–orbit (MESO) device proposed by Manipatruni, Nikonov, Lin, Gosavi, Liu, Prasad, Huang, Bonturim, Ramesh and Young (Nature 565, 35–42, 2019) is a beyond-CMOS logic primitive that writes a nanomagnet's state by magnetoelectric (ferroelectric) switching at a projected ~100 mV and reads it out by spin-to-charge conversion in a high spin–orbit-coupling material, with a projected attojoule-class switching energy per bit and the ability to cascade devices through ordinary charge interconnects. The originating paper is a proposal with projected benchmarks; it explicitly frames a roadmap of unresolved materials, device, circuit, interconnect and manufacturability issues that must be solved before MESO logic becomes a practical technology. Later work has experimentally demonstrated the separate write and readout building blocks and a single integrated MESO device, but the integrated, cascaded core remains open: no experimentally demonstrated cascaded MESO stages or complete majority/NOT logic gates operating at the target voltage and energy exist, and the spin-to-charge output voltages achieved so far (microvolt scale) remain orders of magnitude below what is needed to switch a following stage. The open problem is the experimental realization of the full MESO logic family at its projected operating point, together with the reliability, integration and scaling validation the source roadmap requires.

Background

Complementary metal–oxide–semiconductor (CMOS) transistors have been miniaturized for four decades, but their operating voltage has stalled near the thermal (Boltzmann) limit of charge-based current control, so dimensional scaling no longer brings proportional energy gains. This motivated the search for 'beyond-CMOS' logic switches based on collective internal states (ferroelectric polarization, ferromagnetic magnetization) rather than on charge modulation. The magnetoelectric spin–orbit (MESO) device (Manipatruni et al., Nature 565, 35–42, 2019) is one prominent such proposal from Intel and UC Berkeley. A MESO cell has two coupled transducers. The write node is a magnetoelectric capacitor: switching the ferroelectric polarization of an adjacent multiferroic layer — the prototypical material is bismuth ferrite, BiFeO3, a multiferroic that is both ferroelectric and antiferromagnetic and whose canted antiferromagnetic moment is exchange-coupled (that is, magnetically coupled across the interface) to a soft ferromagnet such as CoFe — rotates the ferromagnet's magnetization without passing a large write current, so the switching energy is set by capacitor charging rather than by Joule heating. The read node uses spin–orbit transduction: a spin-polarized current from the ferromagnet is converted into a charge voltage in a high spin–orbit-coupling material, either by the inverse spin Hall effect (ISHE, conversion of a spin current into a transverse charge voltage in a bulk heavy metal such as Pt) or by the inverse Rashba–Edelstein effect (IREE, interfacial spin-to-charge conversion in a material with Rashba-split or topological surface states, quantified by an effective length λIREE\lambda_{\mathrm{IREE}}). Because both input and output are charge/voltage signals, MESO devices can in principle be cascaded through conventional electrical interconnects — unlike many spintronic proposals that require spin-preserving interconnects — and are non-volatile, giving ultralow standby power. The proposal projects a switching voltage of ~100 mV (a factor of ~5 below CMOS), a switching energy 10–30 times lower than CMOS (attojoule-class, ∼1\sim 1 aJ per bit), 5 times higher logic density, and implementations as majority gates (a three-input logic gate whose output follows the majority of the inputs) plus an inverter (NOT gate), integrated with CMOS peripheral circuitry. The prior experimental status was: voltage control of exchange coupling in CoFe/BiFeO3 had been shown (Manipatruni et al., Science Advances 4, eaat4229, 2018); the ferroelectric switching voltage in La-substituted BiFeO3 had been reduced to ~200 mV in 10-nm films with magnetic coupling surviving to ~5 nm (Prasad et al., Advanced Materials 32, 2001943, 2020); scaled inverse-spin-Hall readout in CoFe/Pt nanostructures had been demonstrated (Pham et al., Nature Electronics 3, 309–315, 2020); and single integrated MESO devices combining a BiFeO3 write with a Pt readout had been reported (Lin et al., IEDM 2019; Vaz et al., IEDM 2021; Vaz et al., Nature Communications 15, 1902, 2024). Circuit-level work (compact models, majority-gate and synchronous circuit design toward 100 mV logic, in-memory computing architectures) has so far been simulation-based. The unresolved question is whether these components can be combined and scaled into the complete, cascaded, low-voltage logic technology the proposal projects.

Problem Statement

Realize, experimentally and at scale, the magnetoelectric spin–orbit (MESO) logic technology proposed by Manipatruni et al. (Nature 565, 35–42, 2019), whose single overarching objective is a complete, cascadable, non-volatile logic family operating at approximately 100 mV with attojoule-class switching energy per bit, integrated with CMOS. The requested results, which are jointly required for this objective and derive from the source paper's roadmap, are: (1) materials — spin–orbit coupling materials (including topological-insulator and oxide two-dimensional-electron-gas systems) whose spin-to-charge conversion efficiency (effective inverse Rashba–Edelstein length λIREE\lambda_{\mathrm{IREE}} and spin-to-charge current ratio) yields output voltages sufficient to switch a following MESO stage, and magnetoelectric/multiferroic thin films with switched polarization and coercive voltage tuned so that ~100 mV deterministic switching is achieved at sub-20-nm lateral dimensions while retaining thermal stability, endurance and interface reproducibility; (2) device reliability — quantified write-error rates, endurance and retention of scaled magnetoelectric–ferromagnet stacks under repeated switching and thermal stress (roadmap targets of order 10^-12 write-error rate); (3) circuit demonstration — experimentally demonstrated cascaded MESO stages and complete majority and NOT logic gates with measured energy and delay including peripheral CMOS drivers, validating the physics-based compact models in integrated circuits, with monolithic or backend-of-line integration compatible with CMOS processing; (4) interconnect and scaling — verification that interconnect resistivity/capacitance and electromigration limits hold for processed full-stack interconnects at high device density, and reproducible sub-10-nm fabrication, patterning and alignment of the multilayer heterostructures with quantified variability impact on circuit yield. The write node, the readout node and a single integrated MESO device have been demonstrated separately, but no cascaded MESO logic or complete logic gate operating at the target voltage and energy has been reported; the spin-to-charge conversion output achieved so far remains orders of magnitude below the level required for cascading. Resolving the task therefore requires the experimental realization of this complete, cascaded logic family at its projected operating point, that is, the four jointly required results above witnessed in fabricated, integrated devices and circuits; a simulation-only cascade, or progress confined to any single one of these four categories, is a partial contribution and does not by itself resolve the task.

References

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