Hayashi, Thomas, Moriya, Rettner and Parkin (Science 320, 209 (2008)) demonstrated the first current-controlled magnetic domain-wall shift register in permalloy nanowires: domain walls (DWs) created, moved and electrically detected by nanosecond spin-polarized current pulses, with cycle times of a few tens of nanoseconds. They identified device-relevant obstacles that define the open problem: the localized field of the injection contact lines inflates the minimum safe DW separation (measured ~2.5 micrometers near zero field, versus a modeled ~0.8 micrometer limit without the contact-line field); inadvertent transverse walls are immobile at the demonstrated current densities and halt shift operations; closely spaced walls annihilate; error probabilities are uncharacterized; and many-bit, low-error operation is undemonstrated. Later literature re-platformed racetrack memory twice — to perpendicular-anisotropy tracks with chiral Neel walls driven by spin-orbit torque, and to synthetic-antiferromagnetic and ferrimagnetic tracks — which circumvented the specific 2008 failure modes in permalloy and partially improved packing and speed, but did not close the core objective. As of the field's 2026 status reviews, reliable device operation (control of stochastic DW behavior, positioning accuracy, integrated readout, 3D scalability at memory-grade error rates) remains the dominant, explicitly open challenge. The objective is therefore quantified, low-error, high-density, many-bit current-controlled domain-wall shift-register operation, in any current-driven track platform.

Background

A magnetic domain wall (DW) is the boundary between regions of uniform magnetization pointing in different directions; in a thin ferromagnetic nanowire magnetized along the wire axis, a head-to-head (or tail-to-tail) wall separates oppositely magnetized domains and can encode a data bit whose position is moved by current, forming a shift register. Two wall structures occur in planar permalloy (NiFe) wires: a vortex wall, in which the magnetization curls around a central core, and a transverse wall, in which the magnetization bends uniformly across the wire width; the two produce different, resolvable changes in the wire's electrical resistance. Spin-transfer torque (STT) is the transfer of angular momentum from a spin-polarized current to the local magnetization, which can push a DW along a wire without external magnetic fields. Hayashi, Thomas, Moriya, Rettner and Parkin used these ingredients in Science 320, 209 (2008) to realize the first current-controlled DW shift register in permalloy nanowires, the experimental building block of the proposed racetrack memory — a non-volatile storage concept, introduced in the companion paper by Parkin, Hayashi and Thomas (Science 320, 190 (2008)), in which many bits are packed along a nanoscopic magnetic track and shifted past read/write elements by short current pulses. In the 2008 device, DWs were injected by the localized Oersted field of a current pulse in a contact line, then driven along a 6 μm6\ \mu\mathrm{m} track segment by STT at current densities of j≈2×108 A/cm2j\approx2\times10^{8}\ \mathrm{A/cm^{2}}, reaching velocities near 150 m/s150\ \mathrm{m/s}; a wall type was inferred from the dc resistance level of the segment. The paper quantified the failure modes that separate the demonstration from a memory device: only vortex walls translated under these pulses, so the inadvertent injection of a transverse wall froze the register; the minimum separation of a neighboring wall pair that avoids mutual annihilation was ~2.5 μm2.5\ \mu\mathrm{m} near zero applied field (sensitive to residual fields below ~0.3 Oe0.3\ \mathrm{Oe}), while a model including the contact-line localized field and magnetostatic wall-wall interactions gave ~0.8 μm0.8\ \mu\mathrm{m} at zero field if the contact-line field were eliminated — an upper bound on bit density; error probabilities from wall-type injection and annihilation were not systematically characterized; and registers with many walls, integrated readout and repeatable timing were not shown. The field subsequently changed platform rather than solving these issues in permalloy: perpendicular-magnetic-anisotropy (PMA) multilayers, in which the interfacial Dzyaloshinskii-Moriya interaction (DMI) — a chiral exchange interaction favoring one wall handedness — makes all DWs homochiral Neel walls, driven efficiently by spin-orbit torque (SOT, the torque exerted by a charge current flowing through a heavy-metal layer with strong spin-orbit coupling), as shown by Miron et al. (2011) and Ryu et al. (2013); and synthetic antiferromagnets (SAFs — two ferromagnetic layers antiferromagnetically coupled through a thin ruthenium spacer), in which compensation of the two layers' magnetostatic moments allows wall velocities up to 750 m/s750\ \mathrm{m/s} with strongly reduced stochastic dispersion (Yang, Ryu and Parkin, 2015), and ferrimagnetic GdFeCo tracks with compensated moments. Reviews by Parkin and Yang (2015), Bläsing et al. (2020), Kumar et al. (2022) and Jeon et al. (2026) track this lineage and consistently identify device reliability, wall positioning accuracy, dense packing, integrated electrical readout (e.g. magnetic tunnel junctions, MTJs — tunneling magnetoresistive sensors — or anomalous-Hall detectors) and three-dimensional integration, rather than the physics of driving walls, as the remaining obstacles to a practical racetrack memory.

Problem Statement

Achieve and quantitatively characterize reliable, high-density operation of a current-controlled magnetic domain-wall shift register — the building block of racetrack memory — as posed by the device obstacles identified in Hayashi et al., Science 320, 209 (2008). Specifically, establish and demonstrate: (1) controlled domain-wall injection, such that every stored wall has a structure that is reliably movable by the write/shift current pulses (or, alternatively, that all wall structures present, including transverse walls, are movable at acceptable current densities), eliminating wall-type-dependent operational failures; (2) a minimum safe separation of neighboring domain walls approaching the intrinsic magnetostatic limit — in the source device, from the measured ~2.5 μm2.5\ \mu\mathrm{m} toward the modeled ~0.8 μm0.8\ \mu\mathrm{m} zero-field value once localized contact-line fields are eliminated — with wall-wall annihilation at small separations prevented or suppressed; (3) write/shift/read error probabilities measured as functions of device geometry, pulse parameters, and residual external field, and reduced to levels consistent with practical memory operation; and (4) consistent, repeatable operation of a many-bit register — long sequences of domain walls at correspondingly higher bit density — with integrated electrical readout. All four sub-goals are jointly required, and resolution is defined by reporting the best-achieved demonstration and its remaining gap to the relevant ideal rather than by attaining an unstated threshold: (1) the demonstrated extent to which injected walls translate under the applied pulses, reporting any wall structures that remain immobile; (2) the best-achieved minimum safe separation and its gap to the zero-field magnetostatic limit modeled for the platform used — the ~0.8 μm0.8\ \mu\mathrm{m} value is the source 2008 permalloy reference only; (3) the measured write/shift/read error probabilities and their gap to practical memory operation, with the intended memory class and its target bit-error-rate order of magnitude stated and justified in the answer; and (4) a register longer than the source's three-bit demonstration, reporting its demonstrated bit count, the shift-sequence length over which operation is repeatable, and the integrated-readout accuracy. The question is platform-general in its objective (the 2008 permalloy-specific failure mechanisms have been superseded by perpendicular-anisotropy, synthetic-antiferromagnetic and ferrimagnetic tracks), so a complete answer in any current-driven domain-wall track platform that meets the density, reliability and scaling conditions above addresses it.

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