As CMOS integrated circuits scale, on-chip interconnect wiring rather than transistors increasingly limits delay and power: copper line resistivity rises sharply as wire width approaches the electron mean free path, wire RC delay per unit length grows while gate delay falls, and crosstalk coupling makes interconnect delay during routing hard to predict. The open problem is a quantitative, predictive model chain for nanoscale interconnect — effective line resistance (surface, grain-boundary, barrier/liner, and roughness scattering in Cu, and the transport physics of alternative conductors such as carbon nanotube bundles, graphene nanoribbons, and alternative metals), wire and coupling capacitance, and the resulting RC and crosstalk-coupled delay from local to global wire lengths — validated by blind prediction against measured test structures and accurate to within 10% of the measured values. Semi-empirical models (Fuchs–Sondheimer/Mayadas–Shatzkes fits, compact CNT/GNR circuit models) exist, but no accepted predictive, multi-material model chain validated at advanced nodes is available; the 2024 IRDS More Moore chapter states interconnect resistance 'has now entered an exponential increase regime' and lists mitigating size effects as a difficult challenge with no identified solution.

Background

On-chip interconnects are the metal wires, fabricated in the back end of line (BEOL, the wiring levels built above the transistors), that carry signals and power between transistors in an integrated circuit. A wire's signal delay is dominated by its RC behavior: the distributed resistance of the conductor charging the wire's capacitance, producing a delay that grows with the square of length for unbuffered wires. As lithographic scaling shrank transistors, gate delay fell from generation to generation while wire RC delay per unit length rose, so interconnects became the primary limiter of chip performance — a point identified by Bohr's IEDM 1995 analysis 'Interconnect scaling—the real limiter to high performance ULSI'.

Traditional delay calculation assumes a constant-resistivity model: resistance equals the bulk metal resistivity times length divided by cross-sectional area. This assumption fails in nanoscale wires. When wire width becomes comparable to the electron mean free path (about 39 nm in copper at room temperature), conduction electrons scatter at the wire surfaces and at grain boundaries (the interfaces between the crystallographic grains of a polycrystalline metal). The classical theories describing these effects are Fuchs–Sondheimer surface scattering, parameterized by a specularity coefficient p (the probability that an electron reflects specularly rather than diffusely at a surface), and Mayadas–Shatzkes grain-boundary scattering, which treats grain boundaries as partially reflecting planes with reflection coefficient R. Steinhögl et al. (Physical Review B, 2002) measured Cu and Al wires down to sub-100-nm widths and showed that a combined Fuchs–Sondheimer/Mayadas–Shatzkes fit with suitable p and R reproduces the steep resistivity rise. In real BEOL wires the situation is harder than in these model experiments: thin barrier/liner layers (diffusion barriers such as TaN that prevent Cu from leaking into surrounding dielectric) consume cross-section and add rough scattering interfaces, and line-edge and sidewall roughness further scatter electrons. The IEEE International Roadmap for Devices and Systems (IRDS), the industry's successor to the International Technology Roadmap for Semiconductors (ITRS), states in its 2024 More Moore chapter that interconnect resistance 'has now entered an exponential increase regime because of non-ideal scaling of barriers for Cu bringing less metallization volume and increased scattering at the surface and grain-boundary interfaces', and lists 'mitigate impact of size effects in interconnect structures' among its difficult challenges.

Because of this size-effect crisis, alternative conductors have been studied intensively: bundles of single-walled carbon nanotubes (CNTs, cylindrical sheets of graphene with ballistic electron transport along the tube), graphene nanoribbons (GNRs, strips of the two-dimensional carbon sheet graphene, whose edges cause additional scattering), and alternative metals (Co, Ru, Mo, and epitaxial metals) whose shorter bulk mean free path or smoother interfaces reduce the size effect. Naeemi and Meindl built compact physics-based circuit models for CNT-bundle and GNR interconnects (IEEE TED 2007, 2009), and Gall's 2020 review 'The search for the most conductive metal for narrow interconnect lines' surveys the alternative-metal landscape, concluding that no drop-in Cu replacement with clearly lower resistivity at small widths has been established.

On the capacitance side, shrinking wire pitch (the center-to-center spacing between adjacent parallel wires) increases coupling capacitance between neighboring wires. This crosstalk couples a wire's delay to the switching activity and routing of its neighbors, so predicting interconnect delay during routing — before neighboring nets are final — becomes a coupled prediction problem rather than a per-wire lookup. Crosstalk-aware routing research (e.g., crosstalk-aware routing resource assignment, Journal of Computer Science and Technology 2005) addressed this by reserving spacing and managing coupling, and it remains an active target: a 2025 ICCAD paper (ChronoTE) still develops learned crosstalk-aware timing estimation specifically for routing optimization, indicating the EDA community treats accurate crosstalk-coupled delay prediction during routing as unsolved.

The threads above — size-effect resistivity physics, RC-delay scaling, crosstalk-coupled delay prediction, and alternative conductors — are the facets of one underlying need expressed across the source literature and the industry roadmap: a quantitative, predictive treatment of nanoscale interconnect resistance, capacitance, and delay that design automation — timing-driven routing (routing that shapes wire paths to meet circuit-speed targets) and static timing analysis (the full-chip check that verifies every signal path against clock constraints without simulating the circuit) — and architecture evaluation can rely on. Existing models are either semi-empirical (fitted scattering parameters, fitted per experiment) or conditional projections for candidate materials; none constitutes an accepted, blind-validated predictive model chain at advanced nodes.

Problem Statement

Construct and validate a quantitative, predictive model chain for nanoscale on-chip interconnect that design automation and architecture evaluation can rely on. Specifically: (1) predict the effective line resistance of scaled on-chip wires at widths comparable to or below the electron mean free path (about 39 nm in Cu at room temperature), including surface scattering, grain-boundary scattering, barrier/liner and line-edge/sidewall roughness effects for Cu, and the corresponding transport physics for candidate alternative conductors such as bundles of single-walled carbon nanotubes (CNTs, cylindrical sheets of graphene with quasi-ballistic electron transport along the tube), graphene nanoribbons (GNRs, strips of the two-dimensional carbon sheet whose edges cause additional scattering), and alternative metals (e.g., Co, Ru, Mo); (2) predict wire and coupling capacitance at scaled pitch; and (3) predict the resulting RC delay and crosstalk-coupled delay for local through global wire lengths, with crosstalk-coupled delay predicted within the routing loop rather than only checked after routing completes. The material set of deliverable (1) is a required minimum rather than an exhaustive enumeration: the chain must cover Cu together with at least one class of candidate alternative conductor — carbon nanotube bundles, graphene nanoribbons, or alternative metals — and may extend to further conductors. The common objective binding these deliverables is a single validated chain from conductor/material physics to interconnect delay: it must be predictive — its scattering and material parameters fixed in advance or derived independently, not refitted to each validation structure — and validated by blind comparison against measured test structures, with effective resistance, capacitance, and delay predicted within 10% of the measured values, and demonstrated by exercising the chain inside a routing or timing-analysis flow; the measured test-structure data for each deliverable (scaled-line effective resistance, scaled-pitch coupling capacitance, and crosstalk-coupled delay) and the routing or timing-analysis flow are to be sourced from the cited works or other public measured test-structure data.

References

  1. Werner Steinhögl, Günther Schindler, Gernot Steinlesberger, Manfred Engelhardt, 'Size-dependent resistivity of metallic wires in the mesoscopic range', Physical Review B 66, 075414 (2002). DOI: 10.1103/PhysRevB.66.075414, https://doi.org/10.1103/PhysRevB.66.075414
  2. A. F. Mayadas and M. Shatzkes, 'Electrical-Resistivity Model for Polycrystalline Films: the Case of Arbitrary Reflection at External Surfaces', Physical Review B 1, 1382–1389 (1970). DOI: 10.1103/PhysRevB.1.1382, https://doi.org/10.1103/PhysRevB.1.1382
  3. M. T. Bohr, 'Interconnect scaling—the real limiter to high performance ULSI', Proceedings of International Electron Devices Meeting (IEDM 1995), pp. 241–244. DOI: 10.1109/IEDM.1995.499187, https://doi.org/10.1109/IEDM.1995.499187
  4. Azad Naeemi and James D. Meindl, 'Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems', IEEE Transactions on Electron Devices 54(1), 26–37 (2007). DOI: 10.1109/TED.2006.887210, https://doi.org/10.1109/TED.2006.887210
  5. Azad Naeemi and James D. Meindl, 'Compact Physics-Based Circuit Models for Graphene Nanoribbon Interconnects', IEEE Transactions on Electron Devices 56(9), 1822–1833 (2009). DOI: 10.1109/TED.2009.2026122, https://doi.org/10.1109/TED.2009.2026122
  6. Daniel Gall, 'The search for the most conductive metal for narrow interconnect lines', Journal of Applied Physics 127(5), 050901 (2020). DOI: 10.1063/1.5133671, https://doi.org/10.1063/1.5133671
  7. Hai-Long Yao, Yi-Ci Cai, Qiang Zhou, Xian-Long Hong, 'Crosstalk-Aware Routing Resource Assignment', Journal of Computer Science and Technology 20(2), 231–236 (2005). DOI: 10.1007/s11390-005-0231-x, https://doi.org/10.1007/s11390-005-0231-x
  8. Leilei Jin, Rongliang Fu, Zhen Zhuang, Liang Xiao, Fangzhou Liu, Bei Yu, Tsung-Yi Ho, 'ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs', 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD). DOI: 10.1109/ICCAD66269.2025.11240759, https://doi.org/10.1109/ICCAD66269.2025.11240759
  9. IEEE, 'International Roadmap for Devices and Systems (IRDS), 2024 Edition, More Moore Chapter', IEEE, 2024. No DOI; verifiable at https://irds.ieee.org/images/files/pdf/2024/2024IRDS_MM.pdf