A silicon junctionless transistor with a gate length of only about 8 nm, defined by helium ion beam lithography and gated by ferroelectric Hf0.5Zr0.5O2, showed strong suppression of short-channel effects — off-state current reduced by roughly two orders of magnitude and a minimum subthreshold swing of 33 mV/dec — attributed to a transient negative capacitance effect in the ferroelectric gate dielectric. What remains unresolved after that 2021 demonstration is whether the negative-capacitance benefit is stable, repeatable, and robust from device to device; what process window (coercive-voltage window, polarization switching near threshold, sensitivity to gate length, ferroelectric thickness, and lithographic dose) sustains it; how it survives endurance, retention, and variability; and whether the simple capacitance-based model generalizes to other ferroelectric stacks, bias conditions, and shorter gates. In short: can ferroelectric negative capacitance reliably suppress short-channel effects in ultimately scaled logic, with a physically validated model, rather than in a single demonstrator.

Background

As metal-oxide-semiconductor field-effect transistors are scaled below a 10 nm gate length, short-channel effects — drain-induced barrier lowering (the drain voltage lowering the source-side potential barrier that gate control depends on), loss of gate control over the off-state current, and degraded subthreshold swing — increasingly dominate device behavior. The subthreshold swing (SS, the gate-voltage change needed for one decade of drain-current change) of a conventional transistor is bounded at room temperature by about 60 mV/dec, a consequence of the Boltzmann distribution of carriers in the semiconductor. Negative capacitance (NC) was proposed by Salahuddin and Datta (2008) as a way around this limit: a ferroelectric material sits at an energy maximum of its Landau double-well free-energy landscape during polarization switching, where its small-signal capacitance is negative, so placing a ferroelectric layer in series with the gate dielectric can amplify the internal gate voltage and steepen switching. Hf0.5Zr0.5O2 (HZO) is the technologically important ferroelectric for this purpose because it is CMOS-compatible and can be deposited as a thin film by atomic layer deposition (a layer-by-layer gas-phase deposition technique that controls film thickness to sub-nanometer precision); however, direct time-domain measurements (Hoffmann et al., 2019) showed that in practice the negative capacitance of such films is usually transient (a dynamic effect during polarization switching) rather than a stabilized steady state, and whether transient NC (TNC) can deliver a usable, hysteresis-free benefit in a transistor has been actively debated (Kobayashi, 2018). In parallel, the junctionless transistor (Colinge et al., 2010) is a device concept in which source, channel, and drain share one doping type, so there are no p-n junctions to leak at short gate lengths — an architecture attractive for extreme scaling. In 2021, Chang et al. combined these ideas: they patterned an about 8 nm TiN (titanium nitride, the gate metal) gate on a Si junctionless transistor by helium ion beam lithography (HIBL, a high-resolution resist-exposure technique using a focused beam of helium ions, here with hydrogen silsesquioxane resist — a resist that converts to silica-like glass where exposed — at a damage-free dose) and compared paraelectric HfO2 against ferroelectric Hf0.5Zr0.5O2 gate oxides. The ferroelectric gate suppressed the off-state current by roughly two orders of magnitude, reduced the minimum SS to 33 mV/dec, and enhanced the on/off ratio in the reverse-sweep direction; a time-domain analysis indicated that a transient negative capacitance effect occurs in the ferroelectric gate dielectric, and the authors proposed a physical model attributing the steep swing to the capacitance increase during ferroelectric polarization switching near the subthreshold region. The steep behavior was tied to the coercive-voltage window (the range of gate voltages over which the ferroelectric layer switches polarization) and appeared directionally (reverse sweep), i.e., hysteretic. What the study did not establish — and what remains unresolved — is whether this negative-capacitance benefit can be made a reliable, designable property of ultimately scaled junctionless logic.

Problem Statement

After the demonstration by Chang et al. (2021) of a ferroelectric Hf0.5Zr0.5O2-gated Si junctionless transistor with an approximately 8 nm gate defined by helium ion beam lithography — in which transient negative capacitance suppressed short-channel effects (off-current down by about two orders of magnitude, minimum subthreshold swing 33 mV/dec, benefit appearing in the reverse sweep) — establish whether ferroelectric negative capacitance can reliably suppress short-channel effects in ultimately scaled junctionless logic. A complete answer must jointly deliver, for sub-10 nm-gate ferroelectric junctionless transistors: (1) experimentally determined stability, repeatability, and device-to-device robustness of the transient negative-capacitance benefit, delivered either as new artifact-controlled time-domain measurements or as a systematic analysis of primary experimental data (measured device data, not a secondary literature review), in both cases documenting measurement-circuit impedance, both sweep directions, and multiple sweep rates; (2) a quantitative process window — the coercive-voltage (the gate voltage at which the ferroelectric layer switches polarization) and polarization-switching conditions relative to the subthreshold region, and the sensitivity of the benefit to gate length, ferroelectric-layer thickness, and lithographic dose; (3) endurance (behavior under repeated polarization cycling, including any wake-up — the drift of switching behavior during initial field cycling — or fatigue dynamics), retention, and variability of the benefit at these dimensions; and (4) a physically validated model that goes beyond the simplified capacitance picture and predicts, rather than merely fits, the observed voltage amplification and steep swing across ferroelectric stacks, bias conditions, and gate lengths at and below 8 nm — that is, it must predict behavior for conditions beyond those used to calibrate it. These components serve one objective — turning the one-off demonstration into reliable, designable negative-capacitance gating at ultimate scaling — and answers claiming only a subset (for example, simulation-only scalability, or reliability on a different platform) do not resolve it. Each component may be grounded in an analysis of primary experimental data from sub-10 nm ferroelectric junctionless devices together with physics-based modeling (original measurements are not required), but simulation-only results do not satisfy components (1)–(3).

References

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