Completing a system-level, uncertainty-quantified benchmarking methodology for beyond-CMOS logic devices

A 2013 uniform benchmarking study by Nikonov and Young produced the first directly comparable estimates of circuit area, switching delay, and switching energy for beyond-CMOS logic technologies (tunneling FETs, spintronic devices, graphene bilayer devices, and others), concluding that tunneling FETs lead the low-power options and that spintronic logic becomes competitive with CMOS if voltage-controlled magnetization switching can be realized. The authors themselves deferred five categories of work needed before their conclusions can be trusted: standby (leakage) power, circuit architectures that exploit nonvolatile state retention, system-level interconnect/clock/sensing overheads, systematic parameter-uncertainty quantification, and validation of the device physics (voltage-controlled switching parameters; the bilayer-graphene exciton condensate assumed by the Bilayer pseudospin FET (BisFET)) underlying the most favorable projections. (These five categories aggregate the six gaps itemized in the Background below, the last category covering gaps (iii) and (iv).) The authors' own 2015 update added first-order leakage treatment and sequential logic but still excluded chip-level clock distribution and any uncertainty analysis, and no later study closes the remaining gaps jointly. The open problem is to complete the methodology into a total-power, architecture-aware, system-level, uncertainty-quantified benchmark with validated or explicitly uncertainty-carrying device-physics inputs, and thereby establish robustly whether any beyond-CMOS logic technology improves on advanced CMOS in energy, delay, and area.

Background

Complementary metal–oxide–semiconductor (CMOS) transistors have been the basis of digital logic for decades, but as dimensional scaling slows, the Nanoelectronics Research Initiative (NRI) funded research on 'beyond-CMOS' logic devices that compute with a state variable other than gate-controlled electronic charge. Examples include tunneling field-effect transistors (TFETs), which switch by quantum-mechanical band-to-band tunneling and can in principle operate at supply voltages below the CMOS floor; spintronic devices, which represent information in the magnetization of nanomagnets and pass it between stages as spin current or spin waves (including nanomagnetic logic, NML, in which chains of nanomagnets are clocked to propagate logic states); and a proposed graphene bilayer device, the Bilayer pseudospin FET (BisFET), whose operation postulates a Bose–Einstein condensate (BEC) of excitons — bound electron–hole pairs forming a coherent collective phase — between two graphene monolayers.

Nikonov and Young (2013) published the first uniform methodology for benchmarking these heterogeneous technologies: for each device they modeled the same circuits (an inverter with fan-out of 4, a 2-input NAND, a 32-bit adder, later extended) and estimated circuit area, switching delay, and switching energy from device-level physics with a pinned, published parameter set — lithography pitch $F$, supply voltage $V_{dd}$, on-current $I_{on}$, a capacitance adjustment factor $M_{\text{cadj}}$ scaling intrinsic device capacitance, and for voltage-controlled switching the multiferroic/magnetoelectric material constants of the layer adjacent to the nanomagnet (remanent polarization $P_{mf}$, effective fields $E_{mf}$ and $B_{mf}$, saturation magnetostriction $B_{ms}$, magnetoelectric coupling $\alpha_{me}$) — releasing the code so results are reproducible. Their headline conclusions were that TFETs are the leading low-power electronic option, and that spintronic devices can implement complex logic functions with fewer elements and become competitive with CMOS if voltage-controlled (magnetoelectric) switching replaces current-controlled switching.

The authors themselves listed the method's principal gaps. (i) Only active switching energy is counted, not standby ('leakage') power — the energy dissipated while a circuit is idle — so technologies with significant leakage are flattered, and architectural mitigations such as power-gating (cutting the supply to idle blocks) are not assessed. (ii) Most spintronic devices are nonvolatile (they retain state with power off), enabling normally-off, instantly-on chips and logic-in-memory architectures in which compute and storage co-locate; the chosen benchmark circuits cannot credit these attributes. (iii) The voltage-controlled switching models rest on optimistic experimental parameter estimates for multiferroic/piezoelectric materials, and fast, reliable, low-voltage switching meeting them was not demonstrated. (iv) The BisFET projections depend on an exciton condensate in bilayer graphene whose critical temperature was — and remains — contested across orders of magnitude, and on interlayer coupling values for which device-grade current–voltage characteristics were unavailable. (v) Long interconnects beyond bit-to-bit length, clock distribution networks, and read/sensing circuits such as sense amplifiers were excluded from the power accounting. (vi) Accuracy was stated as no better than a factor of two, with no systematic sensitivity analysis over the pinned parameters. A predecessor conference paper (Nikonov and Young, International Electron Devices Meeting (IEDM), 2012) established the same methodology in preliminary form; the 2013 paper is the complete, citable statement of it.

Problem Statement

Starting from the Nikonov–Young uniform benchmarking methodology and its 2015 extension, complete it into a system-level, uncertainty-quantified benchmarking methodology for beyond-CMOS logic technologies, and use it to determine robustly whether any beyond-CMOS technology improves on advanced CMOS in total energy (active plus idle), delay, and area at the system level. Here 'advanced CMOS' denotes the pinned CMOS references of the source methodology — CMOS HP taken from the 2011 ITRS PIDS chapter at lithography half-pitch $F=15$ nm (the 2018 column, chosen for the NRI study), with $V_{dd}=0.73$ V, $I_{on}=1805$ A/m, $M_{\text{cadj}}=1$, and CMOS LP as the envisioned 0.3 V low-supply-voltage device of Avci et al. (2011; reference [11] of Ref. 1 below), with $V_{dd}=0.3$ V, $I_{on}=2$ A/m, $M_{\text{cadj}}=1$ — treated, exactly like the beyond-CMOS parameters, as pinned published inputs under the same uniform assumptions; any re-pinning of the CMOS baseline to a later roadmap projection must be made explicit and applied uniformly to all benchmarked devices. The completed methodology must: (1) account for standby (leakage) power together with architectural mitigations such as power-gating, so that total energy — active plus idle — is compared across technologies rather than active switching energy alone; (2) benchmark circuit architectures that exploit nonvolatile state retention (normally-off, instantly-on operation and logic-in-memory) on metrics commensurable with CMOS-based alternatives, so that nonvolatility is credited or debited on the same scale as other attributes; (3) include the system-level contributions excluded from the original benchmarks — long interconnects beyond bit-to-bit length, clock distribution networks, and read/sensing circuits — uniformly across the device suite benchmarked by the methodology (its pinned per-release device set: the 2013 device list together with the 2015 additions); (4) quantify systematically how the rankings and conclusions depend on the pinned but uncertain, correlated input parameters — the per-device $V_{dd}$, $I_{on}$, $M_{\text{cadj}}$, lithography pitch $F$, and the pinned material constants, including the multiferroic/magnetoelectric parameters $P_{mf}$, $E_{mf}/B_{mf}$, $B_{ms}$, $\alpha_{me}$ and the BisFET interlayer-coupling assumptions — identifying which conclusions are robust and which are artifacts of optimistic parameter choices; and (5) for device options whose projected advantage rests on unvalidated physics — fast, reliable, low-voltage voltage-controlled magnetization switching, and a high-temperature exciton condensate in bilayer graphene for the BisFET — either validate the assumed parameters experimentally or carry their uncertainty explicitly through the comparison so that the final verdict does not depend silently on them.

References

1. Dmitri E. Nikonov and Ian A. Young, 'Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking', Proceedings of the IEEE 101(12), 2498–2533 (2013). DOI: 10.1109/jproc.2013.2252317; author manuscript at https://arxiv.org/abs/1302.0244
2. Dmitri E. Nikonov and Ian A. Young, 'Uniform methodology for benchmarking beyond-CMOS logic devices', 2012 International Electron Devices Meeting (IEDM), pp. 25.4.1–25.4.4 (2012). DOI: 10.1109/iedm.2012.6479102; https://doi.org/10.1109/iedm.2012.6479102
3. Dmitri E. Nikonov and Ian A. Young, 'Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits', IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 1, 3–11 (2015). DOI: 10.1109/jxcdc.2015.2418033; https://doi.org/10.1109/jxcdc.2015.2418033
4. Chenyun Pan, Sou-Chi Chang, and Azad Naeemi, 'Performance analyses and benchmarking for spintronic devices and interconnects', 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 56–58 (2016). DOI: 10.1109/iitc-amc.2016.7507679; https://doi.org/10.1109/iitc-amc.2016.7507679
5. Takahiro Hanyu, 'Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor', 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 117–120 (2013). DOI: 10.1109/iscas.2013.6571796; https://doi.org/10.1109/iscas.2013.6571796
6. Sasikanth Manipatruni, Dmitri E. Nikonov, Chia-Ching Lin, Tanay A. Gosavi, Huichu Liu, Bhagwati Prasad, Yen-Lin Huang, Everton Bonturim, Ramamoorthi Ramesh, and Ian A. Young, 'Scalable energy-efficient magnetoelectric spin–orbit logic', Nature 565, 35–42 (2018). DOI: 10.1038/s41586-018-0770-2; https://doi.org/10.1038/s41586-018-0770-2
7. Huichu Liu, Sasikanth Manipatruni, Daniel H. Morris, Kaushik Vaidyanathan, Dmitri E. Nikonov, Tanay Karnik, and Ian A. Young, 'Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin–Orbit Devices Toward 100-mV Logic', IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5(1), 1–9 (2019). DOI: 10.1109/jxcdc.2019.2897598; https://doi.org/10.1109/jxcdc.2019.2897598
8. Xiaomeng Liu, Kenji Watanabe, Takashi Taniguchi, Bertrand I. Halperin, and Philip Kim, 'Quantum Hall drag of exciton condensate in graphene', Nature Physics 13, 746–750 (2017). DOI: 10.1038/nphys4116; https://doi.org/10.1038/nphys4116
9. Jung-Jung Su and Allan H. MacDonald, 'Spatially indirect exciton condensate phases in double bilayer graphene', Physical Review B 95, 045416 (2017). DOI: 10.1103/PhysRevB.95.045416; https://doi.org/10.1103/PhysRevB.95.045416
10. Harley D. Scammell and Oleg P. Sushkov, 'Exciton condensation in biased bilayer graphene', Physical Review Research 5, 043176 (2023). DOI: 10.1103/PhysRevResearch.5.043176; https://doi.org/10.1103/PhysRevResearch.5.043176
11. Hiroyasu Nakayama, Takayuki Nozaki, Toshiki Yamaji, Tomohiro Nozaki, Hiroshi Imamura, and Shinji Yuasa, 'Static magnetization switching in an artificial antiferromagnetic multilayer driven by a voltage-controlled magnetic anisotropy effect', Nature Materials (2026). DOI: 10.1038/s41563-026-02575-w; https://doi.org/10.1038/s41563-026-02575-w
12. Chenyun Pan and Azad Naeemi, 'Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications', arXiv:1711.04295 (2017); https://arxiv.org/abs/1711.04295