Gate-all-around (GAA) nanosheet transistors are the industry-standard successor to FinFETs, and the near-term form of the question 'will transistors stop shrinking' is how far the contacted poly pitch (CPP) — the lateral gate-to-gate repeat distance that sets standard-cell density — can still be reduced before GAA CMOS itself saturates. A 2025 calibrated transport plus design-technology co-optimization study found that Si nanosheet devices allow CPP scaling to roughly 38 nm (about 34 nm with aggressively improved junction abruptness) before nanosheet-thickness scaling gains saturate and contact resistivity limits further shrinkage; an independent 2026 imec study reaches a similar contact-limited minimum CPP of about 36 nm at the A2 node even for atomically thin 2D channels. The surviving open problem is to quantitatively determine the CPP floor for GAA-class CMOS, identify the mechanism that sets the limit at each pitch step, and establish whether the resulting floor is a hard physical/technological boundary or a transient of current contact technology.

Background

Logic CMOS density has for decades been driven by lateral shrinkage of the transistor grid, parameterized in layout by the contacted poly pitch (CPP) — the sum of gate length, spacer thicknesses, and contact length, i.e. the horizontal repeat distance between adjacent transistor gates in a standard cell. The current industry architecture is the gate-all-around (GAA) nanosheet FET, in which the channel is a stack of horizontal silicon sheets fully wrapped by the gate, replacing the FinFET (a vertical silicon fin flanked by a tri-gate) at the 3 nm and subsequent nodes; 'angstrom' nodes (A16, A14, A10, A7, A5, A2...) are the roadmap naming for the generations beyond 3 nm/2 nm. The relevant prior results and conventions are as follows. (1) Electrostatic short-channel control in a nanosheet improves as the sheet thickness TNST_{\mathrm{NS}} decreases, which relaxes the gate-length and spacer requirements; junction abruptness (the sharpness of the source/drain doping transition, denoted δ\delta) plays a similar role. (2) Design-technology co-optimization (DTCO) is the standard methodology that connects calibrated device simulation to standard-cell layout and circuit metrics, so that a pitch limit is expressed as an iso-performance or iso-power-performance-area (PPA) boundary rather than a single device figure of merit. (3) The middle of line (MOL) — the local contacts and via-level interconnect between transistor terminals and the first metal layers — contributes parasitic capacitance and resistance that grows in relative importance as the gate pitch shrinks, and contact resistivity at nanoscale source/drain interfaces is a principal suspect for the eventual floor. (4) Two families of innovations are explicitly proposed in the roadmap literature as scaling extenders: backside power delivery (BSPDN, moving the power distribution network to the wafer backside, which frees frontside routing and reduces IR drop), and vertical integration — the complementary FET (CFET, stacking the n- and p-MOS nanosheet devices of an inverter vertically), forksheet variants (a dielectric wall between n and p regions enabling tighter n-to-p spacing), and replacing silicon channels with atomically thin two-dimensional (2D) semiconductors such as MoS2_2. The most direct prior quantitative result is a December 2025 IEEE Transactions on Electron Devices study (Bhuwalka et al., Huawei/Global TCAD) combining an extensively calibrated transport model with a DTCO flow: it finds that CPP can scale to about 38 nm at a gate length of roughly 10 nm with TNS≈3.5T_{\mathrm{NS}}\approx 3.5 nm, that aggressively improving junction abruptness would allow about 34 nm at a gate length of roughly 6 nm, and that further TNST_{\mathrm{NS}} scaling gains saturate because of severe transport degradation, while contact-length scaling is bounded by middle-of-line and interface resistivity. An imec roadmap presentation (VLSI-TSA 2024) frames the industry expectation as 'slow pitch/track scaling' combined with forksheet/CFET evolution and backside power delivery. What remains unsettled is the ultimate lateral floor — whether the roughly 34–36 nm contact-limited CPP regime now appearing in independent studies is a hard physical/technological floor or a transient of current contact technology.

Problem Statement

Determine, with a device-to-circuit methodology calibrated to experimental data, the minimum contacted poly pitch (CPP) to which gate-all-around nanosheet CMOS can be scaled at iso-performance (or iso-PPA), identifying which mechanism — short-channel electrostatics versus the spacer/gate-length trade-off versus nanosheet thickness and junction-abruptness limits versus contact/middle-of-line resistivity and parasitic capacitance versus variability and self-heating — sets the boundary at each pitch step down to and below the roughly 34-36 nm regime currently reported; and establish whether that regime is a hard physical/technological floor or a transient of current contact-formation technology, or demonstrate the absence of such a floor through a scaling path below it. The iso-performance / iso-PPA criterion is understood in the DTCO convention documented by the cited anchor studies: device/circuit performance held fixed across pitch-scaling steps within an extensively calibrated transport model combined with a DTCO flow that accounts for accurate device and circuit intrinsics and parasitics (Bhuwalka et al., IEEE Trans. Electron Devices 72(12), 6437-6446, 2025), and circuit-level benchmarking against a reference-node target such as the imec A2 convention of delivering the same ring-oscillator frequency as the N2 node with only a modest (~8% per generation) increase in power density, with designs evaluated at matched off-current (IOFF) in a ~1500 nm2^2 standard cell via a 15-stage fan-out-of-3 ring oscillator at VDD = 0.7 V and benchmarked in Ieff/Ceff space against iso-frequency contours (Xi et al., arXiv:2607.12707). The question is the concrete near-term form of whether transistors keep shrinking laterally: an answer must state the reference baseline and target metric it uses for the iso-criterion, the floor (or demonstrate its absence through a scaling path below it), and the limiting mechanism(s), including whether the reported regime is a hard floor or a transient of current contact technology. Backside power delivery and vertical stacking architectures (CFET, forksheet, and their 2D-channel variants) remain roadmap context in which any proposed scaling path below the reported regime may be framed; a binary extend-or-postpone verdict on them is not a required deliverable.

References

  1. Krishna K. Bhuwalka, Lee-Chi Hung, Gerhard Rzepa, Franz Schanovsky, Zlatan Stanojevic, Lei Hou, Wei Li, Markus Karner, Zheng Yu, 'Contacted-Poly-Pitch (CPP) Scaling Limitations of Si Gate-All-Around Nanosheet (GAA-NS) Devices', IEEE Transactions on Electron Devices 72(12), 6437-6446 (2025). DOI: 10.1109/TED.2025.3615917, https://doi.org/10.1109/TED.2025.3615917
  2. Lishu Wu, 'The next generation of gate-all-around transistors', Nature Electronics 6(7), 469 (2023). DOI: 10.1038/s41928-023-01006-x, https://doi.org/10.1038/s41928-023-01006-x
  3. N. Horiguchi, H. Mertens, R. Ritzenthaler, S. Subramanian, P. Weckx, P. Schuddinck, A. Veloso, S. Yang, K. Serbulova, J. Ryckaert, 'CMOS Scaling by Nanosheet Device Architectures and Backside Engineering', 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA) (2024). DOI: 10.1109/VLSITSA60681.2024.10546439, https://doi.org/10.1109/VLSITSA60681.2024.10546439
  4. Fengben Xi, Gautam Gaddemane, Anshul Gupta, Sheng Yang, Aryan Afzalian, Quentin Smets, Maarten Van de Put, Kaustuv Banerjee, Tom Schram, Devin Verreck, Ward Janssens, Juergen Boemmels, Xiangyu Wu, Thomas Chiarella, Jérôme Mitard, Gouri Sankar Kar, Geert Hellings, Cesar Javier Lockhart de la Rosa, 'Are gate-all-around 2D CFETs the optimal architecture for the A2 node and beyond?', arXiv:2607.12707 (submitted 14 July 2026). https://arxiv.org/abs/2607.12707
  5. Shixin Li, Yanna Luo, Haoqing Xu, Jiali Huo, Zhaohai Di, Yongliang Li, Qingzhu Zhang, Huaxiang Yin, Zhenhua Wu, 'Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm', IEEE Transactions on Electron Devices 70(12), 6118-6124 (2023). DOI: 10.1109/TED.2023.3323449, https://doi.org/10.1109/TED.2023.3323449
  6. J. Lee, S. Eom, M. Kim, Y. Ahn, S. Lee, J. Jeong, S. Lee, R.-H. Baek, 'Ultra-Stacked Forksheet-FET and Monolithic Complementary-FET for Å7~5 node Visibility', 2024 IEEE International Electron Devices Meeting (IEDM) (2024). DOI: 10.1109/IEDM50854.2024.10873498, https://doi.org/10.1109/IEDM50854.2024.10873498
  7. Chih-Hao Chang, V.S. Chang, K.H. Pan, K.T. Lai, J.H. Lu, J.A. Ng, C.Y. Chen, B.F. Wu, C.J. Lin, C.S. Liang, C.P. Tsao, Y.S. Mor, C.T. Li, T.C. Lin, C.H. Hsieh, P.N. Chen, H.H. Hsu, J.H. Chen, H.F. Chen, J.Y. Yeh, M.C. Chiang, C.Y. Lin, J.J. Liaw, C.H. Wang, S.B. Lee, C.C. Chen, H.J. Lin, R. Chen, K.W. Chen, C.O. Chui, Y.C. Yeo, K.B. Huang, T.L. Lee, M.H. Tsai, K.S. Chen, Y.C. Lu, S.M. Jang, S.-Y. Wu, 'Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond', 2022 International Electron Devices Meeting (IEDM) (2022). DOI: 10.1109/IEDM45625.2022.10019565, https://doi.org/10.1109/IEDM45625.2022.10019565
  8. Xue Chen, Su-Ting Han, Ye Zhou, 'Scaling the contacted poly pitch of 2D transistors', Nature Electronics 8(5), 378-379 (2025). DOI: 10.1038/s41928-025-01383-5, https://doi.org/10.1038/s41928-025-01383-5