Interface-modified ramp-edge Josephson junctions made from high-critical-temperature cuprate superconductors are the only demonstrated route to single-flux-quantum (SFQ) circuits operating above 30 K, but their critical-current spread across a chip has never been controlled tightly enough for large-scale integration. In the fabrication process of Igarashi et al. (2007), the ramp edge that becomes the junction is defined by a reflowed photoresist profile transferred into the multilayer by ion milling, so the ramp angle — which sets junction area and barrier formation — inherits the resist-edge shape. That shape depends on the surrounding circuit layout: feature sizes and pattern density influence how the resist flows, so identical process conditions yield different ramp angles at different points of a circuit, and suppressing the resulting 'tail' structures previously required extra hard-mask deposition steps. Igarashi et al. (2007) refined the reflow photolithography and demonstrated smooth, tail-free ramps with a small spread in their angles on the mask pattern of a single toggle flip-flop circuit; extending that result so that mask thickness, reflow temperature/time, and circuit geometry are co-optimized to produce uniform resist-edge shapes — and therefore uniform ramp angles — for every feature of a complex circuit, without tails or added hard-mask steps, remains unresolved.

Background

A Josephson junction is a weak link between two superconductors through which a supercurrent flows; in digital single-flux-quantum (SFQ) circuits, voltage pulses each carrying one magnetic flux quantum are routed through thousands to hundreds of thousands of such junctions, which requires all junctions on a chip to have nearly identical critical currents. In high-critical-temperature superconducting (HTS) cuprate technology, the workhorse device is the ramp-edge junction: the base electrode is etched into a sloped step (the ramp), a thin barrier is formed on that slope — in the 'interface-modified' process used by the AIST group, by deliberately disrupting the crystalline surface before counter-electrode deposition — and the junction area is the inclined face. Because junction current density depends on the barrier and the projected area of the ramp, the ramp angle set by lithography directly shapes the junction's electrical parameters. The AIST/Tanabe group's process defined the ramp with a photoresist mask whose profile was rounded by thermal reflow (heating above the glass transition so surface tension smooths the resist edge) and then transferred into the superconducting multilayer by ion milling; the resist-mask thickness and reflow temperature/time control the resulting edge slope, and improper profiles leave unwanted 'tail' structures at the ramp foot, while earlier fixes added a separately deposited hard etch mask (a non-sacrificial masking layer) at the cost of extra process steps. By 2005 this process had reached 100-junction test arrays with a 1-sigma spread of critical currents of 6–17% at 4.2 K and run-to-run reproducibility of about ±12% on average critical current (Wakana et al. 2005), and improvements to counter-electrode deposition (Wakana et al. 2002) attacked spread from the deposition side. Yet complete SFQ circuits demonstrated only up to roughly 200 junctions, versus 100,000 in niobium technology (Tanabe and Hidaka 2007). Even within one chip, the post-reflow resist-edge shape — and hence the ramp angle — varies with circuit layout: the pattern design and the distribution of feature sizes around each element influence how the resist reflows, so uniform junctions across all features of a complex circuit cannot be expected from a single reflow recipe. In Igarashi et al. (2007), optimization of the resist-reflowing parameters was found to be crucially important — excessive reflowing increased the spread in ramp angles — and smooth, tail-free ramps with a small spread in their angles were demonstrated on the mask pattern of a single toggle flip-flop circuit; a single recipe that yields the same reflowed profile at every feature of a complex, layout-heterogeneous circuit was not thereby established.

Problem Statement

Determine how thermal resist reflow couples to circuit-layout geometry — the distribution of feature sizes and pattern density around each element — and use that understanding to co-optimize etch-mask thickness, reflow temperature and time, and circuit pattern design so that a single photolithography recipe produces a uniform reflowed resist-edge shape, and therefore a uniform ramp angle after ion-milling, at every feature of a complex high-Tc ramp-edge-junction circuit — one with the heterogeneous feature sizes and pattern densities around each element that make resist reflow layout-dependent — the uniformity being at least as tight as the small spread in ramp angles demonstrated on the single toggle flip-flop mask pattern in Igarashi et al. (2007), without reintroducing tail structures at the ramp foot and without additional hard-mask deposition steps. A resolution is a validated model of this reflow–layout coupling, together with co-optimized parameter values (etch-mask thickness; reflow temperature and time) and layout-design rules, shown to meet that uniformity across the whole layout — at every feature of a circuit whose feature sizes and pattern densities genuinely vary around each element, not merely at one — with that heterogeneity preserved rather than removed, for example by density homogenization. A predictive, model-based answer meeting this standard resolves the task; a fabricated device demonstration is not required.

References

  1. K. Igarashi, K. Higuchi, H. Wakana, S. Adachi, N. Iwata, H. Yamamoto, K. Tanabe, 'Improvement of ramp fabrication for high-Tc ramp-edge Josephson junction', Physica C 463–465 (2007) 965–968. DOI: 10.1016/j.physc.2007.03.474, https://doi.org/10.1016/j.physc.2007.03.474
  2. H. Wakana, S. Adachi, A. Kamitani, K. Nakayama, Y. Ishimaru, Y. Oshikubo, Y. Tarutani, K. Tanabe, 'Improvement in Reproducibility of Multilayer and Junction Process for HTS SFQ Circuits', IEEE Trans. Appl. Supercond. 15 (2005) 153–156. DOI: 10.1109/TASC.2005.849723, https://doi.org/10.1109/TASC.2005.849723
  3. Hironori Wakana, Seiji Adachi, Masahiro Horibe, Yoshihiro Ishimaru, Yasuo Oshikubo, Yoshinobu Tarutani, Keiichi Tanabe, 'Development of Two-Step Deposition Process for Interface-Modified Ramp-Edge Josephson Junction with Low Sheet Inductance and Small Spread', Jpn. J. Appl. Phys. 41 (2002) L1366–L1369. DOI: 10.1143/JJAP.41.L1366, https://doi.org/10.1143/JJAP.41.L1366
  4. K. Tsubone, Y. Tarutani, H. Wakana, S. Adachi, K. Tanabe, 'Logic Operation of HTS SFQ Logic Family', IEEE Trans. Appl. Supercond. 19 (2009) 3758–3765. DOI: 10.1109/TASC.2009.2024694, https://doi.org/10.1109/TASC.2009.2024694
  5. K. Tanabe, M. Hidaka, 'Recent Progress in SFQ Device Technologies in Japan', IEEE Trans. Appl. Supercond. 17 (2007) 494–499. DOI: 10.1109/TASC.2007.898704, https://doi.org/10.1109/TASC.2007.898704
  6. H. Wakana, S. Adachi, K. Tsubone, K. Igarashi, Y. Tarutani, H. Yamamoto, K. Tanabe, 'Parameter optimization of separated-base layout for HTS SFQ circuits using interface-modified ramp-edge Josephson junctions', Physica C 463–465 (2007) 961–964. DOI: 10.1016/j.physc.2007.04.291, https://doi.org/10.1016/j.physc.2007.04.291
  7. H. Wakana, S. Adachi, K. Nakayama, K. Tsubone, Y. Tarutani, K. Tanabe, 'Fabrication of Ramp-Edge Junctions With High ICRNI_C R_N Products by Using Cu-Poor Precursor', IEEE Trans. Appl. Supercond. 17 (2007) 233–236. DOI: 10.1109/TASC.2007.898694, https://doi.org/10.1109/TASC.2007.898694
  8. S. Döring, S. Schmidt, F. Schmidl, V. Tympel, S. Haindl, F. Kurth, K. Iida, I. Mönch, B. Holzapfel, P. Seidel, 'Edge-type Josephson junctions with Co-doped Ba-122 thin films', Supercond. Sci. Technol. 25 (2012) 084020. DOI: 10.1088/0953-2048/25/8/084020, https://doi.org/10.1088/0953-2048/25/8/084020
  9. S. Adachi, Y. Oshikubo, A. Tsukamoto, Y. Ishimaru, T. Hato, J. Kawano, K. Tanabe, 'Improved reproducible fabrication process of HTS-SQUIDs with ramp-edge Josephson junctions and multilayer structures', Physica C 470 (2010) 1515–1519. DOI: 10.1016/j.physc.2010.05.152, https://doi.org/10.1016/j.physc.2010.05.152
  10. Seiji Adachi, Akira Tsukamoto, Yasuo Oshikubo, Tsunehiro Hato, Keiichi Tanabe, 'Fabrication of HTS ramp-edge-type Josephson junctions and SQUIDs using various YBCO-derivatives as barrier materials', Jpn. J. Appl. Phys. 60 (2021) 093001. DOI: 10.35848/1347-4065/ac1c8e, https://doi.org/10.35848/1347-4065/ac1c8e