Junxu Li (arXiv:2408.06561, 2024) constructed quantum arithmetic logic units — adders, subtractors, multipliers, and dividers — built only from Pauli-X, CNOT, and controlled-sqrt(X) (CSX) gates with every two-qubit gate acting on nearest-neighbor qubits of a two-dimensional square lattice, with ancillas reset for reuse and with support for superposition inputs. The paper's Conclusion and Outlook section explicitly poses four unresolved directions: (1) the minimum qubit connectivity actually required by these circuits and their adaptation to other architectures such as IBM's; (2) efficient readout and algorithmic utilization of the superposition outputs, including when such use yields quantum speedup; (3) optimization of the circuits for compatibility with quantum error correction; and (4) — the direction the paper itself labels an open question — whether the constructions generalize from integer to floating-point arithmetic while retaining only X, CNOT, and CSX gates on neighboring qubits. Directions 1, 3, and 4 remain unaddressed by later work, and direction 2 has only a partial result — the author's own follow-up using superposed adder outputs to prepare linear probability distributions — so all four directions remain open.

Background

A quantum arithmetic logic unit (QALU) is a quantum circuit that realizes an arithmetic operation such as addition or multiplication on qubit registers while respecting the rules of quantum mechanics: the computation must be unitary and reversible, and registers can hold quantum superpositions of many integers at once. On near-term quantum computers — the current generation of noisy devices with tens to a few hundred qubits, often called NISQ (Noisy Intermediate-Scale Quantum) hardware — two hardware constraints dominate circuit design. First, connectivity: not every pair of qubits can interact directly, and on many platforms two-qubit gates are only available between physically adjacent qubits (a nearest-neighbor constraint) defined by the device's coupling graph; IBM superconducting processors, for example, use a heavy-hex lattice rather than a square grid. Second, gate fidelity: multi-qubit gates such as the Toffoli gate (a controlled-controlled-NOT, i.e. a three-qubit gate) are hard to execute faithfully, so designs avoiding them are preferable. Classical-style reversible adders typically rely on Toffoli gates to compute carry bits, which motivated the search for arithmetic decompositions using only one- and two-qubit gates.

Li's 2024 design (arXiv:2408.06561) provides quantum binary adders, subtractors (via the two's-complement representation, in which a negative integer is encoded as its bitwise complement plus one), multipliers, and dividers, all decomposed into only Pauli-X gates (the quantum NOT), CNOT gates (controlled-NOT), and CSX gates — the controlled square-root-of-X gate, a two-qubit gate that applies the sqrt(X) rotation to the target conditional on the control. The trick that replaces Toffoli gates is to accumulate integer and half-integer powers of X on ancilla qubits (extra workspace qubits) initialized to the state ∣0⟩|0\rangle: for example, the carry of a one-bit full adder is produced as XX raised to an exponent built from parities of the input bits, where CSX contributes half-integer terms that always combine to integers. All two-qubit gates act between nearest neighbors on a two-dimensional square lattice of qubits; ancillas are returned to ∣0⟩|0\rangle at the end so they can be reused, which keeps the qubit count low. The circuits accept superposition inputs and map superpositions of basis states to superpositions of the corresponding outputs. A 2026 journal article by the same author (Physica Scripta) restates these constructions for square lattice architectures without resolving the open directions.

Prior quantum floating-point (FP) arithmetic — representing real numbers as a significand (mantissa) scaled by an integer power of a fixed base, with normalization and rounding after each operation — was developed by Häner et al. (arXiv:1807.02023) and Seidel et al. (IEEE Access 2022), but their circuits require long-range two-qubit gates and Toffoli gates, making them unsuitable for near-term hardware. A 2025 work by Cruz Serrallés et al. (arXiv:2510.20145) develops FP arithmetic for fault-tolerant quantum computers, i.e., at the logical level of error-corrected machines rather than under the nearest-neighbor, Toffoli-free constraint set of interest here. Quantum error correction (QEC), such as the surface code — an error-correcting encoding that spreads one logical qubit over a 2D grid of physical qubits — replaces physical gates with logical ones and makes non-Clifford gates (gates outside the group generated by, e.g., CNOT and single-qubit Clifford operations, such as the T gate) expensive, since CSX and other non-Clifford operations require special resources at the logical level. A comprehensive survey of quantum arithmetic circuit design (Wang et al., Phil. Trans. R. Soc. A 2025) situates Li's work within an active synthesis literature, but none of the surveyed lines characterizes minimal connectivity or Toffoli-free FP arithmetic in Li's gate model. The unresolved question is therefore whether Li's X/CNOT/CSX nearest-neighbor framework can be carried from the idealized square-lattice integer setting to the full requirements of practical quantum arithmetic.

Problem Statement

The common objective is to carry Li's quantum-arithmetic framework — QALU circuits built solely from Pauli-X, CNOT, and CSX gates with all two-qubit gates on nearest-neighbor qubits, with ancillas recycled to ∣0⟩|0\rangle and with superposition inputs supported — from its idealized setting (integers, square-lattice connectivity, no error correction) to the full requirements of practical quantum computation. Within this objective, the source poses four sub-questions. Each is an independently resolvable component of that objective and carries its own resolution criterion, stated with it below; the full objective is met only when all four directions are addressed:

  1. Minimum connectivity. Determine the minimum necessary qubit connectivity for the presented QALUs: characterize the connectivity graphs on which the adders, subtractors, multipliers, and dividers can be implemented without changing the gate set (X, CNOT, CSX only) and without introducing SWAP-gate overhead, where minimum is taken under the subgraph partial order — a graph is minimal if no proper subgraph of it admits the same circuits — and give explicit adaptations to the heavy-hex lattices of IBM processors and to linear chains, keeping two-qubit gates nearest-neighbor. This direction is resolved by such a characterization together with an explicit adaptation or a no-go argument for each of these two named topologies.

  2. Utilization of superposition outputs. Since the QALUs map superposition inputs to superposed arithmetic outputs, design efficient measurement and algorithmic strategies to read out and use the output superposition states, and determine whether and when such use produces a quantum algorithmic speedup for named higher-level tasks that rely on these arithmetic units, such as Shor's algorithm or quantum simulation, measured against the best known classical or quantum method for the same task. This direction is resolved by a demonstrated speedup, or by a proof that no speedup arises, for at least one such named task. (The author's own linear-distribution preparation result is a first step; the general readout and speedup question remains.)

  3. Compatibility with quantum error correction. The source focuses on feasibility and does not extensively address noise and errors, while advanced error correction is essential for accurate results: minimize the logical-gate and logical-qubit overhead of the X/CNOT/CSX nearest-neighbor QALUs when they are embedded in a fault-tolerant encoding such as the surface code, including the decomposition of the non-Clifford CSX gate into logical-level operations, and report that overhead relative to the unencoded circuits. This direction is resolved by a logical-level construction whose overhead is so quantified, or by a proven lower bound on the achievable overhead.

  4. Extension from integers to floating point (explicitly labeled an open question by the source): determine whether the nearest-neighbor X/CNOT/CSX primitive set and the ancilla-reuse design can be generalized to implement floating-point addition and multiplication — including significand/exponent handling, alignment, normalization, and rounding, either exactly or for a stated approximate scheme — without long-range gates or Toffoli gates, and evaluate the resource and connectivity tradeoffs. This direction is resolved by an explicit such construction with those tradeoffs quantified, or by a no-go argument showing that the primitive set cannot implement floating-point addition or multiplication. If achievable, such circuits could approximate hard-to-compute functions such as exponentials and logarithms.

References

  1. Junxu Li, A Feasible Design of Elementary Quantum Arithmetic Logic Units for Near-Term Quantum Computers, arXiv:2408.06561 (2024), DOI 10.48550/arXiv.2408.06561, https://arxiv.org/abs/2408.06561
  2. Junxu Li, Prepare Linear Distributions with Quantum Arithmetic Units, Entropy 26(11), 912 (2024), DOI 10.3390/e26110912, https://doi.org/10.3390/e26110912
  3. Junxu Li, Hardware-efficient quantum arithmetic logic units for square lattice architectures, Physica Scripta 101, 105104 (2026), DOI 10.1088/1402-4896/ae4b73, https://doi.org/10.1088/1402-4896/ae4b73
  4. Thomas Häner, Mathias Soeken, Martin Roetteler, Krysta M. Svore, Quantum circuits for floating-point arithmetic, in Reversible Computation, Lecture Notes in Computer Science (Springer, 2018), pp. 162-174, DOI 10.1007/978-3-319-99498-7_11, https://doi.org/10.1007/978-3-319-99498-7_11, arXiv:1807.02023, https://arxiv.org/abs/1807.02023
  5. Raphael Seidel, Nikolay Tcholtchev, Sebastian Bock, Colin Kai-Uwe Becker, Manfred Hauswirth, Efficient Floating Point Arithmetic for Quantum Computers, IEEE Access 10, 72400-72415 (2022), DOI 10.1109/ACCESS.2022.3188251, https://doi.org/10.1109/ACCESS.2022.3188251, arXiv:2112.10537, https://arxiv.org/abs/2112.10537
  6. José E. Cruz Serrallés, Oluwadara Ogunkoya, Doğa Murat Kürkçüoğlu, Nicholas Bornman, Norm M. Tubman, Anna Grassellino, Silvia Zorzetti, Riccardo Lattanzi, Efficient Floating-Point Arithmetic on Fault-Tolerant Quantum Computers, arXiv:2510.20145 (2025), DOI 10.48550/arXiv.2510.20145, https://arxiv.org/abs/2510.20145
  7. Robert A. M. Basili, Wenyang Qian, Shiplu Sarker, Shuo Tang, Austin Castellino, Mary Eshaghian-Wilner, Ashfaq Khokhar, Glenn Luecke, James P. Vary, Performance evaluations of signed and unsigned noisy approximate quantum Fourier arithmetic, The Journal of Supercomputing 81, 1465 (2025), DOI 10.1007/s11227-025-07819-1, https://doi.org/10.1007/s11227-025-07819-1, arXiv:2112.09349, https://arxiv.org/abs/2112.09349
  8. Siyi Wang, Xiufan Li, Wei Jie Bryan Lee, Suman Deb, Eugene Lim, Anupam Chattopadhyay, A comprehensive study of quantum arithmetic circuits, Philosophical Transactions of the Royal Society A 383, 20230392 (2025), DOI 10.1098/rsta.2023.0392, https://doi.org/10.1098/rsta.2023.0392, arXiv:2406.03867, https://arxiv.org/abs/2406.03867