After Dennard voltage scaling ended in the mid-2000s, energy became a first-order constraint in high-performance computing (HPC), motivating searches for architectures more energy-efficient than cache-coherent x86 server chips. Johnsson and Netzer (2016) instrumented the Texas Instruments TMS320C6678 digital-signal-processor (DSP) system-on-chip (SoC) — an eight-core 40 nm part whose on-chip memories act as software-managed scratchpads served by DMA engines rather than caches — and showed that, with explicit DMA choreography and hand-tuned kernels, it attains near-peak STREAM bandwidth (up to 10.20 GB/s of sustained COPY bandwidth at eight active cores, with the energy efficiency peaking at 1.47 GB/J for COPY and SCALE at two active cores) and 77% HPL efficiency (2.92 GF/J), comparing favorably with externally reported figures for contemporary x86 and Blue Gene/Q nodes. The question the authors left open is whether those single-node, two-kernel results generalize across HPC workload classes, and at what software-engineering cost, given an HPC software eco-system the authors describe as quite immature relative to x86. The empirical core — can scratchpad/DMA-based DSP SoCs deliver x86-class energy-to-solution across the breadth of production HPC workloads — remains unanswered in the literature.

Background

Moore's law — the doubling of transistor density per CMOS technology generation — has continued, but Dennard scaling, the simultaneous reduction of supply voltage and device dimensions that kept power density constant, broke down in the mid-2000s. The consequences are flattened clock rates, the shift to multicore dies, and a power wall in which an increasing fraction of a chip cannot be powered on simultaneously (the 'dark silicon' analysis of Esmaeilzadeh et al., 2011); long-run measurements show the resulting slowdown in electrical efficiency of computing (Koomey et al., 2011), and circuit-level accounting shows that energy per operation, especially for off-chip memory access, dominates compute energy and scales only weakly with process node (Horowitz, 2014). Energy efficiency therefore became a first-order objective in HPC architecture, tracked for instance by the Green500 ranking of supercomputers by performance per watt, on which accelerator-based systems came to dominate (Subramaniam et al., 2013; Hennessy and Patterson, 2019).

One candidate architecture class studied in this context is the digital signal processor (DSP) SoC: a chip with multiple very-long-instruction-word (VLIW) cores originally aimed at the embedded and mobile markets, designed for roughly 10% of the power of a contemporary x86 server CPU while retaining much more than 10% of its floating-point capability. The specific subject of the source work is the Texas Instruments TMS320C6678: eight C66x VLIW cores on a 40 nm die, whose core-private L1 and L2 memories can be configured as software-managed scratchpad SRAM rather than hardware-managed caches; an on-chip Enhanced DMA controller (EDMA3) that moves data between external DDR3 memory (DDR3-1333, 10.67 GB/s aggregate bandwidth), a 4 MiB multi-core shared memory used as a staging area, and the scratchpads; and a 50 Gb/s 'Hyperlink' port intended for direct chip-to-chip links in multi-DSP systems. On such a chip there is no hardware cache coherence or prefetching to amortize memory energy: the programmer must orchestrate all data movement explicitly, in exchange for fine control over where every byte is fetched and stored.

The evidence base for the question is a measurement campaign whose components were published in companion papers. Netzer, Johnsson, Ahlin, Stotzer, Varis and Laure (IEEE International Parallel & Distributed Processing Symposium Workshops, IPDPSW 2014) implemented the STREAM memory-bandwidth benchmark on the 6678 evaluation module using EDMA3 strided-block transfers, transfer chaining and multi-buffering with L1/L2 as scratchpads, reaching 5.16, 8.86 and 10.20 GB/s of sustained COPY bandwidth on 1, 2 and 8 cores respectively. Netzer, Johnsson, Ahlin and Laure (Energy Efficient Supercomputing Workshop, E2SC 2014) built the per-rail instrumentation (separately measuring the core/logic rail, the on-chip-memory rail, and the DDR3 rail, with unused cores and peripherals powered down) that makes energy-to-solution attribution, reported as GB/J for memory-bound and GF/J for compute-bound workloads, reliable to better than about 1% for the instrumented parts. Johnsson and Netzer (J. Phys.: Conf. Ser. 762, 2016) consolidated the campaign: with a hand-optimized double-precision matrix-multiply (DGEMM) kernel reaching about 95% of peak and data prefetch performed by the on-chip internal DMA (IDMA) engine into the level-1 (L1) memory, the High-Performance Linpack (HPL) benchmark — the dense LU-factorization benchmark of the TOP500 list — reached 77% peak efficiency and 2.92 GF/J, a result the source states was obtained with un-optimized forward and backsolve phases, versus externally reported figures of about 0.97 GF/J for Intel Sandy Bridge and 2.10 GF/J for Blue Gene/Q. The authors concluded that the 6678 can be a practical, energy-efficient alternative for these two kernels, provided explicit EDMA3-based data management, scratchpad blocking, and hand-vectorized kernels are supplied. What their conclusion leaves open is generality and effort, not scaling or process normalization: the tools provided for the 6678 suffice for efficiencies comparable to x86 for STREAM and HPL and, in the authors' words, 'we conjecture also for many HPC applications'; at the same time 'the software eco-system is quite immature compared to that for x86 architecture based systems', and features that simplify achieving high efficiency on x86 'are not present in the 6678 SoC requiring a greater effort in achieving comparable efficiencies'. As reported, the result rests on two canonical kernels on a single 40 nm node whose comparator figures come from heterogeneous measurement methodologies and from parts on other process nodes — the 22 nm Intel Xeon Phi and E5-2697v2 estimates in the STREAM comparison, and the 32 nm Intel Sandy Bridge and 45 nm Blue Gene/Q (POWER7, not x86) figures in the HPL comparison.

Problem Statement

Determine whether a scratchpad/DMA-based DSP SoC — exemplified by the Texas Instruments TMS320C6678 — can serve as a broadly adoptable, energy-efficient alternative to x86 SoCs in production HPC. The energy-efficiency evidence is instrumented energy-to-solution measurement on the 6678 using the per-rail instrumentation of the source study (GB/J for memory-bound, GF/J for compute-bound workloads); where no source has instrumented a workload class, the answer must state explicitly what evidence substitutes for measurement — an estimate grounded in the source study's measured figures and in the 6678's memory-access movement costs, together with its assumptions — rather than leave that class unaddressed; the engineering-effort evidence is necessarily of a different kind, since developer time, toolchain maturity, portability and maintainability are not instrumented quantities. The single overarching objective is a defensible adoptability judgment; the following jointly supporting results, corresponding to the conjecture and the caveats stated in the source's conclusion, define its evidence base: (1) Workload generality — which HPC application classes beyond the memory-bound STREAM and compute-bound HPL kernels attain energy efficiency comparable to x86-based systems (GB/J, GF/J) on the 6678 under the same EDMA3-based, scratchpad-managed data-movement strategy, thereby testing the authors' conjecture that efficiencies comparable to x86 extend beyond STREAM and HPL to many HPC applications, codes with irregular memory access patterns, communication-heavy parallel applications, and sparse or mixed-precision workloads being illustrative of the classes in scope rather than an exhaustive checklist; (2) Software cost — the engineering effort (developer time, toolchain maturity, portability, maintainability) required to reach these efficiencies relative to x86, given that x86 features which simplify achieving high efficiency are absent from the 6678; this axis is addressed by a comparative account of toolchain maturity, portability and maintainability on both platforms rather than by instrumented figures. Comparisons are made on the same footing as the source study: per-rail instrumented energy-to-solution figures for the 6678 against the externally reported comparator figures used there (for example about 0.97 GF/J for Intel Sandy Bridge HPL, and about 1.20 GB/J estimated for the 22 nm Intel Xeon Phi STREAM result). An answer is complete when these two axes are addressed together with the evidence standards above, so that a qualified reviewer can decide — rather than guess — whether DSP SoCs are adoptable as an energy-efficient x86 alternative for production HPC workloads.

References

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